Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <1558742162-73402-1-git-send-email-fenghua.yu@intel.com> <1558742162-73402-2-git-send-email-fenghua.yu@intel.com>
In-Reply-To: <1558742162-73402-2-git-send-email-fenghua.yu@intel.com>
From:   Andy Lutomirski <luto@amacapital.net>
Date:   Thu, 30 May 2019 07:37:34 -0700
Message-ID: <CALCETrWOUCOaEct4EA65WfZ-ZbmB6N8s-1aHNvH6rdKhPJ-CPg@mail.gmail.com>
Subject: Re: [PATCH v3 1/5] x86/cpufeatures: Enumerate user wait instructions
To:     Fenghua Yu <fenghua.yu@intel.com>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        H Peter Anvin <hpa@zytor.com>,
        Andrew Cooper <andrew.cooper3@citrix.com>,
        Ashok Raj <ashok.raj@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Fri, May 24, 2019 at 5:05 PM Fenghua Yu <fenghua.yu@intel.com> wrote:
>
> umonitor, umwait, and tpause are a set of user wait instructions.
>
> umonitor arms address monitoring hardware using an address. The
> address range is determined by using CPUID.0x5. A store to
> an address within the specified address range triggers the
> monitoring hardware to wake up the processor waiting in umwait.
>
> umwait instructs the processor to enter an implementation-dependent
> optimized state while monitoring a range of addresses. The optimized
> state may be either a light-weight power/performance optimized state
> (C0.1 state) or an improved power/performance optimized state
> (C0.2 state).
>
> tpause instructs the processor to enter an implementation-dependent
> optimized state C0.1 or C0.2 state and wake up when time-stamp counter
> reaches specified timeout.
>
> The three instructions may be executed at any privilege level.
>
> The instructions provide power saving method while waiting in
> user space. Additionally, they can allow a sibling hyperthread to
> make faster progress while this thread is waiting. One example of an
> application usage of umwait is when waiting for input data from another
> application, such as a user level multi-threaded packet processing
> engine.
>
> Availability of the user wait instructions is indicated by the presence
> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
>
> Detailed information on the instructions and CPUID feature WAITPKG flag
> can be found in the latest Intel Architecture Instruction Set Extensions
> and Future Features Programming Reference and Intel 64 and IA-32
> Architectures Software Developer's Manual.
>

Reviewed-by: Andy Lutomirski <luto@kernel.org>

> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> Reviewed-by: Ashok Raj <ashok.raj@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 75f27ee2c263..b8bd428ae5bc 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -322,6 +322,7 @@
>  #define X86_FEATURE_UMIP               (16*32+ 2) /* User Mode Instruction Protection */
>  #define X86_FEATURE_PKU                        (16*32+ 3) /* Protection Keys for Userspace */
>  #define X86_FEATURE_OSPKE              (16*32+ 4) /* OS Protection Keys Enable */
> +#define X86_FEATURE_WAITPKG            (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
>  #define X86_FEATURE_AVX512_VBMI2       (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
>  #define X86_FEATURE_GFNI               (16*32+ 8) /* Galois Field New Instructions */
>  #define X86_FEATURE_VAES               (16*32+ 9) /* Vector AES */
> --
> 2.19.1
>


-- 
Andy Lutomirski
AMA Capital Management, LLC