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From:   Jann Horn <jannh@google.com>
Date:   Fri, 31 May 2019 22:37:52 +0200
Message-ID: <CAG48ez0pEHOskDK53LMQa=gbUSoztWR3SuAeux-aVeh_896w5Q@mail.gmail.com>
Subject: Re: [RFC PATCH v2 11/12] x86/mm/tlb: Use async and inline messages
 for flushing
To:     Nadav Amit <namit@vmware.com>
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Andy Lutomirski <luto@kernel.org>,
        Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@intel.com>,
        Ingo Molnar <mingo@redhat.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        "the arch/x86 maintainers" <x86@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>
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On Fri, May 31, 2019 at 10:04 PM Nadav Amit <namit@vmware.com> wrote:
> > On May 31, 2019, at 12:20 PM, Jann Horn <jannh@google.com> wrote:
> > On Fri, May 31, 2019 at 8:29 PM Nadav Amit <namit@vmware.com> wrote:
> >> [ +Jann Horn ]
> >>
> >>> On May 31, 2019, at 3:57 AM, Peter Zijlstra <peterz@infradead.org> wr=
ote:
> >>>
> >>> On Thu, May 30, 2019 at 11:36:44PM -0700, Nadav Amit wrote:
> >>>> When we flush userspace mappings, we can defer the TLB flushes, as l=
ong
> >>>> the following conditions are met:
> >>>>
> >>>> 1. No tables are freed, since otherwise speculative page walks might
> >>>>  cause machine-checks.
> >>>>
> >>>> 2. No one would access userspace before flush takes place. Specifica=
lly,
> >>>>  NMI handlers and kprobes would avoid accessing userspace.
> > [...]
> >> A #MC might be caused. I tried to avoid it by not allowing freeing of
> >> page-tables in such way. Did I miss something else? Some interaction w=
ith
> >> MTRR changes? I=E2=80=99ll think about it some more, but I don=E2=80=
=99t see how.
> >
> > I don't really know much about this topic, but here's a random comment
> > since you cc'ed me: If the physical memory range was freed and
> > reallocated, could you end up with speculatively executed cached
> > memory reads from I/O memory? (And if so, would that be bad?)
>
> Thanks. I thought that your experience with TLB page-freeing bugs may
> be valuable, and you frequently find my mistakes. ;-)
>
> Yes, speculatively executed cached reads from the I/O memory are a concer=
n.
> IIRC they caused #MC on AMD. If page-tables are not changes, but only PTE=
s
> are changed, I don=E2=80=99t see how it can be a problem. I also looked a=
t the MTRR
> setting code, but I don=E2=80=99t see a concrete problem.

Can the *physical memory range* not be freed and assigned to another
device? Like, when you mess around with memory hotplug and PCI hotplug?