Received: by 2002:a25:ab43:0:0:0:0:0 with SMTP id u61csp1702671ybi; Sat, 1 Jun 2019 02:56:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxnWjGr7r/z1tBalyyHjLpnNXPPEV32K2iZqsWVEDfUoXehJ5PHg/xOX/Lsx9GYmcsuy7XR X-Received: by 2002:a17:902:7883:: with SMTP id q3mr14918286pll.89.1559382988768; Sat, 01 Jun 2019 02:56:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559382988; cv=none; d=google.com; s=arc-20160816; b=droSJ/a9mTWoce5NJm9IfWaMotpoZqR9RbBvrKq7wCDwpKi0BtfCVGzQCO85qHVSS8 70Kd7hLnJPeH7trR6cP3Tc8p1HHZarHPuYHpFRc5uCyh7rtZqyVX9QTga51vzI/KDVyU tysDyhycixeiKLvTEzfyuBN90DzqF3444MBZdImSGjMEdH0R7skfplwPCP8s5FSAelF5 FIpKuyezKJy7IK0AoHtfjvAYvTQq0q+e+JzmdUyvFbh33vY3EjjSBjHzWIS4Tkwly/fn Tn97eNmDAnqusUoeQ5d/Vhf0+Xdlp3vQpyEsyQTJyA09Epar9d0YHLEQH4GuZ83xT7UM p2bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=3100vxP/UsmTkrRA1PWf29ztikaazO6HoZqpIG36pH0=; b=EqMpfZbgD+SMMVbpMJkPtst6wFYWdG+ahktOoixr+7vkRJgjh/+BOtxXiQgEyY/ZGN a2qXP4TOM4mLd0/tPbe5MfnQwcJqtOj/rte+iQNBGJ2Sd5PTmR0AsT0KBhG3+Jq9PKJl nst4qDaAaE0jY3LebmVUmPtnmjTdPB+/kijifEYEgi7sIrodnzmNB6roupEPB73p7zLr ZND8NPTpS2rp0e05sr78ThFz8SKZ/ay2XoDiO6uNX3VxprMIxVhWbvEWW62d0aHi6z7L FL3x1UoJOy9iUQ1Klq/FIpLql91CzfPdW4Z+4PdeOE5Hxde8nHn1pYQi0FvEY7VfvxFl XpYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6si8601111pgb.41.2019.06.01.02.56.12; Sat, 01 Jun 2019 02:56:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727119AbfFAJwu (ORCPT + 99 others); Sat, 1 Jun 2019 05:52:50 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:60855 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726109AbfFAJwu (ORCPT ); Sat, 1 Jun 2019 05:52:50 -0400 X-UUID: 8202367f81544584ba94eed0d7c71e82-20190601 X-UUID: 8202367f81544584ba94eed0d7c71e82-20190601 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1421988198; Sat, 01 Jun 2019 17:52:43 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 1 Jun 2019 17:52:40 +0800 Received: from mszsdaap41.mediatek.inc (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sat, 1 Jun 2019 17:52:39 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , , David Airlie , Matthias Brugger CC: Jitao Shi , Thierry Reding , Ajay Kumar , Inki Dae , Rahul Sharma , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , , Subject: [v4 1/3] dt-bindings: display: mediatek: update dsi supported chips Date: Sat, 1 Jun 2019 17:52:33 +0800 Message-ID: <20190601095235.9194-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20190601095235.9194-1-jitao.shi@mediatek.com> References: <20190601095235.9194-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update device tree binding documentation for the dsi for Mediatek MT8183 SoCs. Signed-off-by: Jitao Shi Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index fadf327c7cdf..bb3dcd2d8571 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- 2.12.5