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[209.132.180.67]) by mx.google.com with ESMTP id p3si11069918plq.78.2019.06.01.10.24.00; Sat, 01 Jun 2019 10:24:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fdXIboJG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbfFARWq (ORCPT + 99 others); Sat, 1 Jun 2019 13:22:46 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:45354 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726143AbfFARWp (ORCPT ); Sat, 1 Jun 2019 13:22:45 -0400 Received: by mail-lf1-f67.google.com with SMTP id u10so3389961lfm.12 for ; Sat, 01 Jun 2019 10:22:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yD3/2nMu40iWkCJApa1un3cbczzFbKdO9B0J2VVf/BQ=; b=fdXIboJGEs9ESGymq78yu8qUEGAMvfm1YFl7lJvcJq74hnBGstgi3nh1Ht7YV0Ckm4 XZ8/FKCIUqFbF3v+mtlW8LWp3BuPT8bjmcahkROSYSZ+unuhb8849YDQDon13YS/gZfp uqWhz3jP9iZ+94jHeB0wTBPQfgfM6Pu0642rIFbomK/rrAllD8V5JoaaDMLqZQR/p5uT +XXXicxvkrcPkwk79q4OPIxeqDLvbxQrMBWbUjjiOHV7zOwrgtn0YYyGP5/11yMmrN3N bKZby/3X/rUyhnTaBnkGhFORTADk5zbD/ISe7q3l0wAQJGUCu8b5HZys81i0NHgpcqJB l7YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yD3/2nMu40iWkCJApa1un3cbczzFbKdO9B0J2VVf/BQ=; b=lKAVR8tdJO27wf6x87YHaYAyXgCbS60nJ9R29T3wmUaZw1pYlP6YSW9F4fOKj8ysWM Wh0K9sbTBwAs5R+Ld0MO8o+eAqFksFkNknR8dum5jopIz4eU4M5/6shnChDiiSN/E+ZA n6lYnRQOkM+nDERPhx7M6lZkQyNzRqilwrbTCu0U3N8Sto8Y7a2U/PMdSZGAODQ14aHn NiCXHA2FNBI+B8y02UtO2J+1srNWr38+Jsnm73M0bpx8eXUyxtOY4+JdL514enq5YzxG EIZPx6i8Fq0HPfxTc5mtBLxd1KLYmrFsIyEbqfc+Dlobv2o2H4BQgCGOYcWEoaFv1H5c BNtw== X-Gm-Message-State: APjAAAXOaCGICuqkvUmadxqN976CmSES3Ytd1WF6JMe16m2BG7H0NVhL yftwSLTub2PRu0aely/NElx/uE3YkSz/jZi8eYj2fA== X-Received: by 2002:a19:6a01:: with SMTP id u1mr7439447lfu.141.1559409763924; Sat, 01 Jun 2019 10:22:43 -0700 (PDT) MIME-Version: 1.0 References: <1558007594-14824-1-git-send-email-kyarlagadda@nvidia.com> <1558007594-14824-2-git-send-email-kyarlagadda@nvidia.com> In-Reply-To: <1558007594-14824-2-git-send-email-kyarlagadda@nvidia.com> From: Linus Walleij Date: Sat, 1 Jun 2019 19:22:32 +0200 Message-ID: Subject: Re: [PATCH V3 2/4] pinctrl: tegra: Support 32 bit register access To: Krishna Yarlagadda Cc: "thierry.reding@gmail.com" , Jon Hunter , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , linux-tegra@vger.kernel.org, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Peter De Schrijver , Joseph Lo , Suresh Mangipudi , Laxman Dewangan , vidyas@nvidia.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 16, 2019 at 1:53 PM Krishna Yarlagadda wrote: > Tegra194 chip has 32 bit pinctrl registers. Existing register defines in > header are only 16 bit. > Modified common pinctrl-tegra driver to support 32 bit registers of > Tegra 194 and later chips. > > Signed-off-by: Krishna Yarlagadda Patch applied. Yours, Linus Walleij