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From:   Abel Vesa <abel.vesa@nxp.com>
To:     Anson Huang <anson.huang@nxp.com>
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Subject: Re: [PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
Thread-Topic: [PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
Thread-Index: AQHVGaxevUMbLPz7GEiRBakv1/ckCqaJiQoA
Date:   Mon, 3 Jun 2019 07:30:20 +0000
Message-ID: <20190603073018.j236j57ooc7t5hp6@fsr-ub1664-175>
References: <20190603013503.40626-1-Anson.Huang@nxp.com>
 <20190603013503.40626-2-Anson.Huang@nxp.com>
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On 19-06-03 09:35:02, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>=20
> This patch adds i.MX8MN clock driver support.
>=20
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> Changes since V1:
> 	- add GPIOx clocks.

...

> +static struct imx_pll14xx_clk imx8mn_sys_pll __initdata =3D {
> +		.type =3D PLL_1416X,
> +		.rate_table =3D imx8mn_pll1416x_tbl,
> +};
> +
> +static const char *pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy", "du=
mmy", };

All of these should be "static const char * const ".

> +static const char *audio_pll1_bypass_sels[] =3D {"audio_pll1", "audio_pl=
l1_ref_sel", };
> +static const char *audio_pll2_bypass_sels[] =3D {"audio_pll2", "audio_pl=
l2_ref_sel", };

...

> +	clk_data.clks =3D clks;
> +	clk_data.clk_num =3D ARRAY_SIZE(clks);
> +	ret =3D of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +	if (ret < 0) {
> +		pr_err("failed to register clks for i.MX8MN\n");
> +		return -EINVAL;
> +	}
> +
> +	imx_register_uart_clocks(uart_clks);
> +
> +	return 0;
> +}
> +CLK_OF_DECLARE_DRIVER(imx8mn, "fsl,imx8mn-ccm", imx8mn_clocks_init);

Any reason why this cannot be a platform driver ?

> --=20
> 2.7.4
> =