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From:   "Shivamurthy Shastri (sshivamurthy)" <sshivamurthy@micron.com>
To:     Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
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Subject: [PATCH v3 07/12] mtd: spinand: turn SPI NAND to support parameter
 page detection
Thread-Topic: [PATCH v3 07/12] mtd: spinand: turn SPI NAND to support
 parameter page detection
Thread-Index: AdUaBZEnl1jU+7xBQUOxHRT5yHw9jA==
Date:   Mon, 3 Jun 2019 12:43:35 +0000
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Instantiate onfi_helper object for SPI NAND.
Enable SPI NAND core to detect SPI NANDs with parameter page.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
---
 drivers/mtd/nand/spi/core.c | 103 ++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 4c15bb58c623..b031c4a2cdf9 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -400,6 +400,100 @@ static int spinand_lock_block(struct spinand_device *=
spinand, u8 lock)
 	return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
 }
=20
+/**
+ * spinand_read_param_page_op - Read parameter page operation
+ * @base: the nand device
+ * @page: page number where parameter page tables can be found
+ * @buf: buffer used to store the parameter page
+ * @len: length of the buffer
+ *
+ * Read parameter page
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+static int spinand_parameter_page_read(struct nand_device *base,
+				       u8 page, void *buf, unsigned int len)
+{
+	struct spinand_device *spinand =3D nand_to_spinand(base);
+	struct spi_mem_op pread_op =3D SPINAND_PAGE_READ_OP(page);
+	struct spi_mem_op pread_cache_op =3D
+				SPINAND_PAGE_READ_FROM_CACHE_OP(false,
+								0,
+								1,
+								buf,
+								len);
+	u8 feature;
+	u8 status;
+	int ret;
+
+	if (len && !buf)
+		return -EINVAL;
+
+	ret =3D spinand_read_reg_op(spinand, REG_CFG,
+				  &feature);
+	if (ret)
+		return ret;
+
+	/* CFG_OTP_ENABLE is used to enable parameter page access */
+	feature |=3D CFG_OTP_ENABLE;
+
+	spinand_write_reg_op(spinand, REG_CFG, feature);
+
+	ret =3D spi_mem_exec_op(spinand->spimem, &pread_op);
+	if (ret)
+		return ret;
+
+	ret =3D spinand_wait(spinand, &status);
+	if (ret < 0)
+		return ret;
+
+	ret =3D spi_mem_exec_op(spinand->spimem, &pread_cache_op);
+	if (ret)
+		return ret;
+
+	ret =3D spinand_read_reg_op(spinand, REG_CFG,
+				  &feature);
+	if (ret)
+		return ret;
+
+	feature &=3D ~CFG_OTP_ENABLE;
+
+	spinand_write_reg_op(spinand, REG_CFG, feature);
+
+	return 0;
+}
+
+static int check_version(struct nand_device *base,
+			 struct nand_onfi_params *p, int *onfi_version)
+{
+	/*
+	 * SPI NANDs do not necessarily support ONFI standard,
+	 * but, parameter page looks the same as an ONFI table.
+	 */
+	if (!le16_to_cpu(p->revision))
+		*onfi_version =3D 0;
+
+	return 0;
+}
+
+static int spinand_intf_data(struct nand_device *base,
+			     struct nand_onfi_params *p)
+{
+	return 0;
+}
+
+static int spinand_param_page_detect(struct spinand_device *spinand)
+{
+	struct nand_device *base =3D spinand_to_nand(spinand);
+
+	base->helper.page =3D 0x01;
+	base->helper.check_revision =3D check_version;
+	base->helper.parameter_page_read =3D spinand_parameter_page_read;
+	base->helper.init_intf_data =3D spinand_intf_data;
+
+	return nand_onfi_detect(base);
+}
+
 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 sta=
tus)
 {
 	struct nand_device *nand =3D spinand_to_nand(spinand);
@@ -910,6 +1004,15 @@ static int spinand_detect(struct spinand_device *spin=
and)
 		return ret;
 	}
=20
+	if (!spinand->base.memorg.pagesize) {
+		ret =3D spinand_param_page_detect(spinand);
+		if (ret <=3D 0) {
+			dev_err(dev, "no parameter page for %*phN\n",
+				SPINAND_MAX_ID_LEN, spinand->id.data);
+			return -ENODEV;
+		}
+	}
+
 	if (nand->memorg.ntargets > 1 && !spinand->select_target) {
 		dev_err(dev,
 			"SPI NANDs with more than one die must implement ->select_target()\n");
--=20
2.17.1