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Tue, 4 Jun 2019 06:56:46 -0700 Received: from [172.23.62.223] (helo=xhdrdevl203.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hY9vh-00054P-Oj; Tue, 04 Jun 2019 06:56:46 -0700 From: Vishal Sagar To: Hyun Kwon , Laurent Pinchart , Mauro Carvalho Chehab , Michal Simek , Rob Herring , Mark Rutland Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Dinesh Kumar , Sandip Kothari , Vishal Sagar Subject: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem Date: Tue, 4 Jun 2019 19:25:55 +0530 Message-Id: <1559656556-79174-2-git-send-email-vishal.sagar@xilinx.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1559656556-79174-1-git-send-email-vishal.sagar@xilinx.com> References: <1559656556-79174-1-git-send-email-vishal.sagar@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39860400002)(346002)(376002)(136003)(396003)(2980300002)(199004)(189003)(4720700003)(4326008)(76176011)(478600001)(110136005)(86362001)(7696005)(51416003)(70586007)(16586007)(14444005)(316002)(70206006)(2906002)(107886003)(9786002)(36386004)(11346002)(186003)(77096007)(63266004)(44832011)(36756003)(26005)(48376002)(356004)(6666004)(50226002)(50466002)(81166006)(81156014)(106002)(305945005)(2616005)(54906003)(476003)(486006)(126002)(8936002)(336012)(8676002)(446003)(47776003)(5660300002)(426003);DIR:OUT;SFP:1101;SCL:1;SRVR:BYAPR02MB4935;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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The Xilinx UHD-SDI Receiver Subsystem consists of SMPTE UHD-SDI (RX) IP core, an SDI RX to Video Bridge IP core to convert SDI video to native video and a Video In to AXI4-Stream IP core to convert native video to AXI4-Stream. Signed-off-by: Vishal Sagar --- .../bindings/media/xilinx/xlnx,sdirxss.txt | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt new file mode 100644 index 0000000..8445bee --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt @@ -0,0 +1,80 @@ + +Xilinx SMPTE UHD-SDI Receiver Subsystem Device Tree Bindings +------------------------------------------------------------ + +The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create systems +based on SMPTE SDI protocols. It receives unaligned native SDI streams from +the SDI GT PHY and outputs an AXI4-Stream video stream, native video, or +native SDI using Xilinx transceivers as the physical layer. + +The subsystem consists of +1 - SMPTE UHD-SDI Rx +2 - SDI Rx to Native Video Bridge +3 - Video In to AXI4-Stream Bridge + +The subsystem can capture SDI streams in utpo 12G mode and output a dual pixel +per clock YUV 422 or 420 10 bits per component AXI4-Stream. + +Required properties: +-------------------- +- compatible: Must contain "xlnx,v-smpte-uhdsdi-rx-ss" +- reg: Physical base address and length of the registers set for the device. +- interrupts: Contains the interrupt line number. +- clocks: List of phandles to AXI4-Lite clock, core clock to SMPTE UHD-SDI Rx + and Video clocks. +- clock-names: Must contain "s_axi_aclk", "sdi_rx_clk" and "video_out_clk" in + the same order as clocks listed in clocks property. +- xlnx,line-rate: The maximum mode supported by the design. Possible values are + are as below - + 12G_SDI_8DS - 12G mode + 6G_SDI - 6G mode + 3G_SDI - 3G mode + +Optional properties: +-------------------- +- xlnx,include-edh: This is present when the Error Detection and Handling + processor is enabled in design. + +Ports +----- +The device node shall contain one 'port' child node as defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Generally the SDI port is connected to a device like SDI Broadcast camera which +is independently controlled. Hence port@0 is a source port which can be +connected to downstream IP which can work with AXI4 Stream data. + +Required port properties: +------------------------- +- reg: 0 - for source port. + +- xlnx,video-format: This can be XVIP_VF_YUV_422 or XVIP_VF_YUV_420. +- xlnx,video-width: This is should be 10. + +Example: + v_smpte_uhdsdi_rx_ss: v_smpte_uhdsdi_rx_ss@80000000 { + compatible = "xlnx,v-smpte-uhdsdi-rx-ss"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,include-edh; + xlnx,line-rate = "12G_SDI_8DS"; + clocks = <&clk_1>, <&si570_1>, <&clk_2>; + clock-names = "s_axi_aclk", "sdi_rx_clk", "video_out_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = ; + xlnx,video-width = <10>; + + sdirx_out: endpoint { + remote-endpoint = <&vcap_sdirx_in>; + }; + }; + }; + }; -- 1.8.3.1