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[209.132.180.67]) by mx.google.com with ESMTP id cj14si20166980plb.141.2019.06.05.04.21.50; Wed, 05 Jun 2019 04:22:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727495AbfFELUZ (ORCPT + 99 others); Wed, 5 Jun 2019 07:20:25 -0400 Received: from foss.arm.com ([217.140.101.70]:57812 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727363AbfFELUZ (ORCPT ); Wed, 5 Jun 2019 07:20:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ADF07374; Wed, 5 Jun 2019 04:20:24 -0700 (PDT) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7EDB53F5AF; Wed, 5 Jun 2019 04:20:24 -0700 (PDT) Received: by e110455-lin.cambridge.arm.com (Postfix, from userid 1000) id D81B6682412; Wed, 5 Jun 2019 12:20:22 +0100 (BST) Date: Wed, 5 Jun 2019 12:20:22 +0100 From: Liviu Dudau To: "Lowry Li (Arm Technology China)" Cc: "james qian wang (Arm Technology China)" , "maarten.lankhorst@linux.intel.com" , "seanpaul@chromium.org" , "airlied@linux.ie" , Brian Starkey , "Julien Yin (Arm Technology China)" , "Jonathan Chai (Arm Technology China)" , Ayan Halder , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , nd Subject: Re: [PATCH v1 2/2] dt/bindings: drm/komeda: Adds SMMU support for D71 devicetree Message-ID: <20190605112022.GU15316@e110455-lin.cambridge.arm.com> References: <1556605118-22700-1-git-send-email-lowry.li@arm.com> <1556605118-22700-3-git-send-email-lowry.li@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1556605118-22700-3-git-send-email-lowry.li@arm.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 30, 2019 at 07:19:34AM +0100, Lowry Li (Arm Technology China) wrote: > Updates the device-tree doc about how to enable SMMU by devicetree. > > Signed-off-by: Lowry Li (Arm Technology China) Reviewed-by: Liviu Dudau Best regards, Liviu > --- > Documentation/devicetree/bindings/display/arm,komeda.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm,komeda.txt > index 02b2265..b12c045 100644 > --- a/Documentation/devicetree/bindings/display/arm,komeda.txt > +++ b/Documentation/devicetree/bindings/display/arm,komeda.txt > @@ -11,6 +11,10 @@ Required properties: > - "pclk": for the APB interface clock > - #address-cells: Must be 1 > - #size-cells: Must be 0 > +- iommus: configure the stream id to IOMMU, Must be configured if want to > + enable iommu in display. for how to configure this node please reference > + devicetree/bindings/iommu/arm,smmu-v3.txt, > + devicetree/bindings/iommu/iommu.txt > > Required properties for sub-node: pipeline@nq > Each device contains one or two pipeline sub-nodes (at least one), each > @@ -44,6 +48,9 @@ Example: > interrupts = <0 168 4>; > clocks = <&dpu_mclk>, <&dpu_aclk>; > clock-names = "mclk", "pclk"; > + iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, > + <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, > + <&smmu 8>, <&smmu 9>; > > dp0_pipe0: pipeline@0 { > clocks = <&fpgaosc2>, <&dpu_aclk>; > -- > 1.9.1 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯