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Subject: Re: [RFC PATCH v2 11/12] x86/mm/tlb: Use async and inline messages for flushing
From:   Andy Lutomirski <luto@amacapital.net>
In-Reply-To: <B41673A7-6CA3-440D-87AA-59E07BE8B656@vmware.com>
Date:   Fri, 7 Jun 2019 09:42:14 -0700
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Andy Lutomirski <luto@kernel.org>,
        Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@intel.com>,
        Ingo Molnar <mingo@redhat.com>,
        Thomas Gleixner <tglx@linutronix.de>, X86 ML <x86@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>
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Message-Id: <B830032A-C36C-44F4-B790-922E6C572704@amacapital.net>
References: <20190531063645.4697-1-namit@vmware.com> <20190531063645.4697-12-namit@vmware.com> <CALCETrU0=BpGy5OQezQ7or33n-EFgBVDNe5g8prSUjL2SoRAwA@mail.gmail.com> <5F153080-D7A7-4054-AB4A-AEDD5F82E0B9@vmware.com> <48CECB5C-CA5B-4AD0-9DA5-6759E8FEDED7@amacapital.net> <67BFA611-F69E-4AE4-A03F-2EF546DC291A@vmware.com> <B41673A7-6CA3-440D-87AA-59E07BE8B656@vmware.com>
To:     Nadav Amit <namit@vmware.com>
Sender: linux-kernel-owner@vger.kernel.org
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On Jun 6, 2019, at 10:28 PM, Nadav Amit <namit@vmware.com> wrote:

>> On May 31, 2019, at 3:07 PM, Nadav Amit <namit@vmware.com> wrote:
>>=20
>>> On May 31, 2019, at 2:47 PM, Andy Lutomirski <luto@amacapital.net> wrote=
:
>>>=20
>>>=20
>>> On May 31, 2019, at 2:33 PM, Nadav Amit <namit@vmware.com> wrote:
>>>=20
>>>>> On May 31, 2019, at 2:14 PM, Andy Lutomirski <luto@kernel.org> wrote:
>>>>>=20
>>>>>> On Thu, May 30, 2019 at 11:37 PM Nadav Amit <namit@vmware.com> wrote:=

>>>>>> When we flush userspace mappings, we can defer the TLB flushes, as lo=
ng
>>>>>> the following conditions are met:
>>>>>>=20
>>>>>> 1. No tables are freed, since otherwise speculative page walks might
>>>>>> cause machine-checks.
>>>>>>=20
>>>>>> 2. No one would access userspace before flush takes place. Specifical=
ly,
>>>>>> NMI handlers and kprobes would avoid accessing userspace.
>>>>>=20
>>>>> I think I need to ask the big picture question.  When someone calls
>>>>> flush_tlb_mm_range() (or the other entry points), if no page tables
>>>>> were freed, they want the guarantee that future accesses (initiated
>>>>> observably after the flush returns) will not use paging entries that
>>>>> were replaced by stores ordered before flush_tlb_mm_range().  We also
>>>>> need the guarantee that any effects from any memory access using the
>>>>> old paging entries will become globally visible before
>>>>> flush_tlb_mm_range().
>>>>>=20
>>>>> I'm wondering if receipt of an IPI is enough to guarantee any of this.=

>>>>> If CPU 1 sets a dirty bit and CPU 2 writes to the APIC to send an IPI
>>>>> to CPU 1, at what point is CPU 2 guaranteed to be able to observe the
>>>>> dirty bit?  An interrupt entry today is fully serializing by the time
>>>>> it finishes, but interrupt entries are epicly slow, and I don't know
>>>>> if the APIC waits long enough.  Heck, what if IRQs are off on the
>>>>> remote CPU?  There are a handful of places where we touch user memory
>>>>> with IRQs off, and it's (sadly) possible for user code to turn off
>>>>> IRQs with iopl().
>>>>>=20
>>>>> I *think* that Intel has stated recently that SMT siblings are
>>>>> guaranteed to stop speculating when you write to the APIC ICR to poke
>>>>> them, but SMT is very special.
>>>>>=20
>>>>> My general conclusion is that I think the code needs to document what
>>>>> is guaranteed and why.
>>>>=20
>>>> I think I might have managed to confuse you with a bug I made (last min=
ute
>>>> bug when I was doing some cleanup). This bug does not affect the perfor=
mance
>>>> much, but it might led you to think that I use the APIC sending as
>>>> synchronization.
>>>>=20
>>>> The idea is not for us to rely on write to ICR as something serializing=
. The
>>>> flow should be as follows:
>>>>=20
>>>>=20
>>>> CPU0                    CPU1
>>>>=20
>>>> flush_tlb_mm_range()
>>>> __smp_call_function_many()
>>>> [ prepare call_single_data (csd) ]
>>>> [ lock csd ]=20
>>>> [ send IPI ]
>>>> (*)
>>>> [ wait for csd to be unlocked ]
>>>>                 [ interrupt ]
>>>>                 [ copy csd info to stack ]
>>>>                 [ csd unlock ]
>>>> [ find csd is unlocked ]
>>>> [ continue (**) ]
>>>>                 [ flush TLB ]
>>>>=20
>>>>=20
>>>> At (**) the pages might be recycled, written-back to disk, etc. Note th=
at
>>>> during (*), CPU0 might do some local TLB flushes, making it very likely=
 that
>>>> CSD will be unlocked by the time it gets there.
>>>>=20
>>>> As you can see, I don=E2=80=99t rely on any special micro-architectural=
 behavior.
>>>> The synchronization is done purely in software.
>>>>=20
>>>> Does it make more sense now?
>>>=20
>>> Yes.  Have you benchmarked this?
>>=20
>> Partially. Numbers are indeed worse. Here are preliminary results, compar=
ing
>> to v1 (concurrent):
>>=20
>>    n_threads    before        concurrent    +async
>>    ---------    ------        ----------    ------
>>    1        661        663        663
>>    2        1436        1225 (-14%)    1115 (-22%)
>>    4        1571        1421 (-10%)    1289 (-18%)
>>=20
>> Note that the benefit of =E2=80=9Casync" would be greater if the initiato=
r does not
>> flush the TLB at all. This might happen in the case of kswapd, for exampl=
e.
>> Let me try some micro-optimizations first, run more benchmarks and get ba=
ck
>> to you.
>=20
> So I ran some more benchmarking (my benchmark is not very suitable), and t=
ried
> more stuff that did not help (checking for more work before returning from=
 the
> IPI handler, and avoid redundant IPIs in such case).
>=20
> Anyhow, with a fixed version, I ran a more standard benchmark on DAX:
>=20
> $ mkfs.ext4 /dev/pmem0
> $ mount -o dax /dev/pmem0 /mnt/mem
> $ cd /mnt/mem
> $ bash -c 'echo 0 > /sys/devices/platform/e820_pmem/ndbus0/region0/namespa=
ce0.0/block/pmem0/dax/write_cache=E2=80=99
> $ sysbench fileio --file-total-size=3D3G --file-test-mode=3Drndwr    \
>    --file-io-mode=3Dmmap --threads=3D4 --file-fsync-mode=3Dfdatasync prepa=
re
> $ sysbench fileio --file-total-size=3D3G --file-test-mode=3Drndwr    \
>    --file-io-mode=3Dmmap --threads=3D4 --file-fsync-mode=3Dfdatasync run
>=20
> ( as you can see, I disabled the write-cache, since my machine does not ha=
ve
>  clwb/clflushopt and clflush appears to become a bottleneck otherwise )
>=20
>=20
> The results are:
>                events (avg/stddev)
>                -------------------
> base                1263689.0000/11481.10
> concurrent            1310123.5000/19205.79    (+3.6%)
> concurrent + async        1326750.2500/24563.61    (+4.9%)
>=20
> So which version do you want me to submit? With or without the async part?=


I think it would be best to submit it without the async part. You can always=
 submit that later.