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[209.132.180.67]) by mx.google.com with ESMTP id 20si3147566pgn.543.2019.06.08.15.55.33; Sat, 08 Jun 2019 15:56:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=pdgoeXaL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727709AbfFHWwR (ORCPT + 99 others); Sat, 8 Jun 2019 18:52:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:33154 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727486AbfFHWwR (ORCPT ); Sat, 8 Jun 2019 18:52:17 -0400 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 189352168B for ; Sat, 8 Jun 2019 22:52:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560034336; bh=Pb4a399ucftTpDo6qRynJAFaW8nxXbV16dTjIDsmmFM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=pdgoeXaLjiEfOp2G++DJMZFPdLAZyPL8dmqY+dDlziJHcN8t9F+Gjg64QOqUpmwfy z3tFad1TjwkL32RkiazMsQhoeKnjq7GS0E3oBmlE7KqbfeUjr7+/M06hTWh7LDiPt5 OHk0LwrdvIvhZ7PQbAinxIC9Q8wE1MX4kyQbPIGQ= Received: by mail-wm1-f47.google.com with SMTP id h19so6491083wme.0 for ; Sat, 08 Jun 2019 15:52:16 -0700 (PDT) X-Gm-Message-State: APjAAAW7metLclkoepgNou24SMcv1IDWYryMJylvJMruoHxe7jKZR9yN xorIf4cyjY0O6uNnJSkJk3Hex/qhOFu4L2x8K/5Ipg== X-Received: by 2002:a1c:a942:: with SMTP id s63mr8242341wme.76.1560034334733; Sat, 08 Jun 2019 15:52:14 -0700 (PDT) MIME-Version: 1.0 References: <1559944837-149589-1-git-send-email-fenghua.yu@intel.com> <1559944837-149589-4-git-send-email-fenghua.yu@intel.com> In-Reply-To: <1559944837-149589-4-git-send-email-fenghua.yu@intel.com> From: Andy Lutomirski Date: Sat, 8 Jun 2019 15:52:03 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/5] x86/umwait: Add sysfs interface to control umwait C0.2 state To: Fenghua Yu Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Andy Lutomirski , Ashok Raj , Tony Luck , Ravi V Shankar , linux-kernel , x86 Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 7, 2019 at 3:10 PM Fenghua Yu wrote: > > C0.2 state in umwait and tpause instructions can be enabled or disabled > on a processor through IA32_UMWAIT_CONTROL MSR register. > > +static u32 get_umwait_control_c02(void) > +{ > + return umwait_control_cached & MSR_IA32_UMWAIT_CONTROL_C02; > +} > + > +static u32 get_umwait_control_max_time(void) > +{ > + return umwait_control_cached & MSR_IA32_UMWAIT_CONTROL_MAX_TIME; > +} > + I'm not convinced that these helpers make the code any more readable.