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[209.132.180.67]) by mx.google.com with ESMTP id h63si8864160pfb.90.2019.06.09.15.08.05; Sun, 09 Jun 2019 15:08:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g+6Vbl0i; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725933AbfFIWHA (ORCPT + 99 others); Sun, 9 Jun 2019 18:07:00 -0400 Received: from mail-lj1-f172.google.com ([209.85.208.172]:45363 "EHLO mail-lj1-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729386AbfFIWHA (ORCPT ); Sun, 9 Jun 2019 18:07:00 -0400 Received: by mail-lj1-f172.google.com with SMTP id m23so6137930lje.12 for ; Sun, 09 Jun 2019 15:06:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=50GXZwDHzCmpvzbBJ8yBES+uMhcVk2V2rV15ilN2B0c=; b=g+6Vbl0iiwSmN9H6YowhpGLJ73aounTBDzKhwymCbPXUe3YFtgu1z4wNCKLkILsZs/ FKkBcFH//l4EcaLCokbemf+udf2+h3MZo4BZFRGYU0k7TFa+hJCq1VGJB8Umrkcd98kp lkU4Vk37IHqN9wT2FoTtsaWc4lSpIcqfaJWjxgoAuWi5z29YyrlYWbhjuKr84CHN2XUL C2Bgw1IznFw2WLjGRQbyFjkn0b3MoPs5N/0e4hn/Gacris0AR8lDHFeUzYiZwq4bXQfE jk4STLcb4kxRKe1TPxcO+kpC+f7ibP9nIBlvBlZvmdNUtRzohvJfxSy8G4TpJbomtPW1 PR3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=50GXZwDHzCmpvzbBJ8yBES+uMhcVk2V2rV15ilN2B0c=; b=stExb5rvWz91XnrnoX9Ej6SAe0xzleSxFnl6eZ9kbNQxtDPesCf1pg8Z7+hKyjgqIa YTIiZngky+wdjQ361jHxX5M+xtyUWb92KtKZZHCsFi8wUM+bXDeU42X0KvDz+mLeiwqM wLhRs5RudWxFFFy+/XYvzwHFD+l1QyNRc3gMybYlnFF8BtXVU8/numgSvTK2vXrI5ri6 rHCGFz9EftjVmv7juIsxWmLx+XG15ppfHaOIwSYW7avQXQBL+ExMmaG2FnNnCxVTkFoa +e6ZKUF2oFAY9xaXwgQe+OB5+NwUo4J9IiqQcJb3MgcWXg5i5MVi4ad+g6MHfUy3oUSe GIpg== X-Gm-Message-State: APjAAAXjYCxtUvHIFlcD6TfHHaNEGa7b0UymZLNkU8foaAXMSLzXqPNj y1GhMGT9sB7G5C1cQ4LSDW/DNk7E1rnCcbqzUtTLGQ== X-Received: by 2002:a2e:5bdd:: with SMTP id m90mr25061179lje.46.1560118018248; Sun, 09 Jun 2019 15:06:58 -0700 (PDT) MIME-Version: 1.0 References: <20190609180621.7607-1-martin.blumenstingl@googlemail.com> <20190609180621.7607-6-martin.blumenstingl@googlemail.com> In-Reply-To: From: Linus Walleij Date: Mon, 10 Jun 2019 00:06:51 +0200 Message-ID: Subject: Re: [RFC next v1 5/5] arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line To: Martin Blumenstingl Cc: netdev , "open list:GPIO SUBSYSTEM" , "open list:ARM/Amlogic Meson..." , Bartosz Golaszewski , Giuseppe CAVALLARO , Alexandre TORGUE , Jose Abreu , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "David S. Miller" , Linux ARM , "linux-kernel@vger.kernel.org" , Kevin Hilman , Neil Armstrong Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jun 9, 2019 at 11:36 PM Martin Blumenstingl wrote: > > If "snps,reset-active-low" was set it results in the sequence 1, 0, 1 > > if it is not set it results in the sequence 0, 1, 0. > > I'm changing this logic with earlier patches of this series. > can you please look at these as well because GPIO_OPEN_SOURCE doesn't > work with the old version of stmmac_mdio_reset() that you are showing. OK but the logic is the same, just that the polarity handling is moved into gpiolib. > > The high (reset) is asserted by switching the pin into high-z open drain > > mode, which happens by switching the line into input mode in some > > cases. > > > > I think the real reason it works now is that reset is actually active high. > > let me write down what I definitely know so far > > the RTL8211F PHY wants the reset line to be LOW for a few milliseconds > to put it into reset mode. > driving the reset line HIGH again takes it out of reset. > > Odroid-N2's schematics [0] (page 30) shows that there's a pull-up for > the PHYRSTB pin, which is also connected to the NRST signal which is > GPIOZ_15 Looks correct, R143 is indeed a pull up indicating that the line is open drain, active low. > > It makes a lot of sense, since if it resets the device when set as input > > (open drain) it holds all devices on that line in reset, which is likely > > what you want as most GPIOs come up as inputs (open drain). > > A pull-up resistor will ascertain that the devices are in reset. > > my understanding is that the pull-up resistor holds it out of reset > driving GPIOZ_15's (open drain) output LOW pulls the signal to ground > and asserts the reset Yep that seems correct. Oh I guess it is this: amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-gpio = <&gpio GPIOZ_15 GPIO_OPEN_SOURCE>; snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; Can you try: snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ? Open source is nominally (and rarely) used for lines that are active high. For lines that are active low, we want to use open drain combined with active low. Yours, Linus Walleij