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[209.132.180.67]) by mx.google.com with ESMTP id ay3si8261718plb.298.2019.06.09.20.45.36; Sun, 09 Jun 2019 20:46:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387548AbfFJDpO (ORCPT + 99 others); Sun, 9 Jun 2019 23:45:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:24926 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387457AbfFJDpN (ORCPT ); Sun, 9 Jun 2019 23:45:13 -0400 X-UUID: b2bb53f8932f442ca9a3f478ae319eea-20190610 X-UUID: b2bb53f8932f442ca9a3f478ae319eea-20190610 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 740195698; Mon, 10 Jun 2019 11:44:56 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Jun 2019 11:44:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 10 Jun 2019 11:44:55 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd CC: James Liao , Fan Chen , , , , , , , Weiyi Lu , Biao Huang Subject: [RFC v1] clk: core: support clocks that need to be enabled during re-parent Date: Mon, 10 Jun 2019 11:44:53 +0800 Message-ID: <1560138293-4163-1-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When using property assigned-clock-parents to assign parent clocks, core clocks might still be disabled during re-parent. Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled during re-parent. Signed-off-by: Weiyi Lu --- drivers/clk/clk.c | 9 +++++++++ include/linux/clk-provider.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 443711f..b2e6fe3 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1717,6 +1717,10 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *core, clk_core_prepare_enable(parent); } + /* enable core if CLK_OPS_CORE_ENABLE is set */ + if (core->flags & CLK_OPS_CORE_ENABLE) + clk_core_prepare_enable(core); + /* migrate prepare count if > 0 */ if (core->prepare_count) { clk_core_prepare_enable(parent); @@ -1744,6 +1748,10 @@ static void __clk_set_parent_after(struct clk_core *core, clk_core_disable_unprepare(old_parent); } + /* re-balance ref counting if CLK_OPS_CORE_ENABLE is set */ + if (core->flags & CLK_OPS_CORE_ENABLE) + clk_core_disable_unprepare(core); + /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */ if (core->flags & CLK_OPS_PARENT_ENABLE) { clk_core_disable_unprepare(parent); @@ -2973,6 +2981,7 @@ static int clk_dump_show(struct seq_file *s, void *data) ENTRY(CLK_IS_CRITICAL), ENTRY(CLK_OPS_PARENT_ENABLE), ENTRY(CLK_DUTY_CYCLE_PARENT), + ENTRY(CLK_OPS_CORE_ENABLE), #undef ENTRY }; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index bb6118f..39a1fed 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -34,6 +34,7 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +#define CLK_OPS_CORE_ENABLE BIT(14) /* core need enable during re-parent */ struct clk; struct clk_hw; -- 1.8.1.1.dirty