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[209.132.180.67]) by mx.google.com with ESMTP id r185si8580720pgr.10.2019.06.09.22.09.24; Sun, 09 Jun 2019 22:09:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=IQZPplZ6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387611AbfFJFJK (ORCPT + 99 others); Mon, 10 Jun 2019 01:09:10 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15235 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387452AbfFJFJJ (ORCPT ); Mon, 10 Jun 2019 01:09:09 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 09 Jun 2019 22:09:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 09 Jun 2019 22:09:08 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 09 Jun 2019 22:09:08 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Jun 2019 05:09:07 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Jun 2019 05:09:07 +0000 Received: from dhcp-10-19-65-14.client.nvidia.com (Not Verified[10.19.65.14]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 09 Jun 2019 22:09:07 -0700 From: Bitan Biswas To: Laxman Dewangan , Thierry Reding , Jonathan Hunter , , , , Peter Rosin , Wolfram Sang , Dmitry Osipenko CC: Shardar Mohammed , Sowjanya Komatineni , Mantravadi Karthik , Bitan Biswas Subject: [PATCH V3 4/6] i2c: tegra: add spinlock definition comment Date: Sun, 9 Jun 2019 22:08:42 -0700 Message-ID: <1560143324-21754-4-git-send-email-bbiswas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560143324-21754-1-git-send-email-bbiswas@nvidia.com> References: <1560143324-21754-1-git-send-email-bbiswas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560143348; bh=3cpCcddyT2qPq3Wnu1Z2qlvBOHM7S82lD9AAMomje2Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=IQZPplZ6jbvcW4yHWCwQtnFJQNywyWyZsoxy58ZfrOV+hhOtQSgZ/qLkXs/kOITpk 6A/naBKyfX9z2ERkYQdCaHVF6BVzfy0ckdovnr3oqyt2SHM2jpNgVEiVXtd9b5ce5G XdYjj+Z31yfqykfsj4BCIWmkUGSDiU97aN1/gYayo6k7eh+re7787ktyOkxZbK+yKd sXe0SOC9fw8LO599dShdj8emcqlxQkKOKOuvmITCy7URKzdQfZYSGbr4+Bz4Wd+JeQ qABjCoO3VHpxwM69RSlX3ePqJGfrmis0MThfvkL3MuwtSwdRJWnkoGNGE9YIZgt3hj L/DzZe84Djkvg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix checkpatch.pl CHECK as follows: CHECK: spinlock_t definition without comment + spinlock_t xfer_lock; Signed-off-by: Bitan Biswas Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2d381de..bececa6 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -269,6 +269,7 @@ struct tegra_i2c_dev { u32 bus_clk_rate; u16 clk_divisor_non_hs_mode; bool is_multimaster_mode; + /* xfer_lock: lock to serialize transfer submission and processing */ spinlock_t xfer_lock; struct dma_chan *tx_dma_chan; struct dma_chan *rx_dma_chan; -- 2.7.4