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[209.132.180.67]) by mx.google.com with ESMTP id u21si10510603pgi.430.2019.06.10.12.28.39; Mon, 10 Jun 2019 12:28:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389010AbfFJT2e (ORCPT + 99 others); Mon, 10 Jun 2019 15:28:34 -0400 Received: from mga18.intel.com ([134.134.136.126]:2978 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728276AbfFJT2e (ORCPT ); Mon, 10 Jun 2019 15:28:34 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jun 2019 12:28:33 -0700 X-ExtLoop1: 1 Received: from sai-dev-mach.sc.intel.com ([143.183.140.153]) by orsmga003.jf.intel.com with ESMTP; 10 Jun 2019 12:28:33 -0700 Message-ID: Subject: Re: [PATCH 5/6] iommu/vt-d: Cleanup after delegating DMA domain to generic iommu From: Sai Praneeth Prakhya To: "Mehta, Sohil" , "joro@8bytes.org" , "baolu.lu@linux.intel.com" , "dwmw2@infradead.org" Cc: "linux-kernel@vger.kernel.org" , "Raj, Ashok" , "cai@lca.pw" , "jacob.jun.pan@linux.intel.com" , "iommu@lists.linux-foundation.org" , "Pan, Jacob jun" , "Tian, Kevin" Date: Mon, 10 Jun 2019 12:25:31 -0700 In-Reply-To: <1560192412.27481.12.camel@intel.com> References: <20190609023803.23832-1-baolu.lu@linux.intel.com> <20190609023803.23832-6-baolu.lu@linux.intel.com> <1560192412.27481.12.camel@intel.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5-0ubuntu0.18.10.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2019-06-10 at 11:45 -0700, Mehta, Sohil wrote: > On Sun, 2019-06-09 at 10:38 +0800, Lu Baolu wrote: > > static int __init si_domain_init(int hw) > > @@ -3306,14 +3252,13 @@ static int __init init_dmars(void) > > if (pasid_supported(iommu)) > > intel_svm_init(iommu); > > #endif > > - } > > > > - /* > > - * Now that qi is enabled on all iommus, set the root entry > > and flush > > - * caches. This is required on some Intel X58 chipsets, > > otherwise the > > - * flush_context function will loop forever and the boot > > hangs. > > - */ > > - for_each_active_iommu(iommu, drhd) { > > + /* > > + * Now that qi is enabled on all iommus, set the root > > entry and > > + * flush caches. This is required on some Intel X58 > > chipsets, > > + * otherwise the flush_context function will loop > > forever and > > + * the boot hangs. > > + */ > > iommu_flush_write_buffer(iommu); > > iommu_set_root_entry(iommu); > > iommu->flush.flush_context(iommu, 0, 0, 0, > > DMA_CCMD_GLOBAL_INVL); > > This changes the intent of the original code. As the comment says > enable QI on all IOMMUs, then flush the caches and set the root entry. > The order of setting the root entries has changed now. > > Refer: > Commit a4c34ff1c029 ('iommu/vt-d: Enable QI on all IOMMUs before > setting root entry') Thanks Sohil! for catching the bug. Will send a V2 to Lu Baolu fixing this. Regards, Sai