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[209.132.180.67]) by mx.google.com with ESMTP id x22si10701551pgj.271.2019.06.10.15.27.30; Mon, 10 Jun 2019 15:27:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=anjqADdv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390152AbfFJWZ4 (ORCPT + 99 others); Mon, 10 Jun 2019 18:25:56 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:39458 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388328AbfFJWZ4 (ORCPT ); Mon, 10 Jun 2019 18:25:56 -0400 Received: by mail-pg1-f195.google.com with SMTP id 196so5764919pgc.6 for ; Mon, 10 Jun 2019 15:25:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=message-id:mime-version:content-transfer-encoding:in-reply-to :references:from:cc:subject:to:user-agent:date; bh=9hBqZJD2Tz09wfOJDUxIvJB/XBCbBflZm3IPa1V/vxE=; b=anjqADdvlUHgxpXTA/xLq/4vsfjEG1pLhPFxuBOoSnhDfQK/DLla5XumwWWyElC6Pc PS/vAaTAZ0X4ENtlyOgXM52+IXMmYlK/mrW38hordPGkJpua0G7qIjeRrGDafXtUX4JO TTshciiU8SjktCILESKUC21nDTZENol6TjYeY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:mime-version :content-transfer-encoding:in-reply-to:references:from:cc:subject:to :user-agent:date; bh=9hBqZJD2Tz09wfOJDUxIvJB/XBCbBflZm3IPa1V/vxE=; b=OrCBXWp3aZWba2gOfqi04bw05e2pZhYncUwdP1QO6ENYhOoZkgUBgY7UofjOmjzFlh qDMIdfQSHrPZyRxksmiohWajJA/g5ZWulPpsm9yl6lj93u2T/x8QsM6MQREq3/RviPd8 zgfWdN+nFSohh9CbpQjGAq0w0hORHu7Tu6Ey44GoLOcwSMkICmxnMMpbrL5v775oTIRj uMQiR9tXZmAHJ0aabmCRiLrzyZwHWm+cxIQIaUcSKaSx/OS0aAYFJiNXByRdixNCVEF8 ZYjCzuREFia9176D5ybI/gUtryZhbSoICj8+oZzTM5ADztc54VShrc3Uep6QMwVefd34 qHTA== X-Gm-Message-State: APjAAAVW1P/JKYsPu/U06qKfdmufHreo+5eCdbPR3EJFHflIrsJPUjCv 6MvC50gfLP/GP9WplUrTglYHGg== X-Received: by 2002:aa7:8219:: with SMTP id k25mr79051964pfi.38.1560205555034; Mon, 10 Jun 2019 15:25:55 -0700 (PDT) Received: from chromium.org ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id v138sm8863906pfc.15.2019.06.10.15.25.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:25:54 -0700 (PDT) Message-ID: <5cfed8f2.1c69fb81.1dcd3.27c1@mx.google.com> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20190429035515.73611-1-drinkcat@chromium.org> <20190429035515.73611-3-drinkcat@chromium.org> <155778659317.14659.136626364818483852@swboyd.mtv.corp.google.com> <155786487644.14659.17142525593824613967@swboyd.mtv.corp.google.com> From: Stephen Boyd Cc: "moderated list:ARM/Mediatek SoC support" , Sean Wang , Linus Walleij , Matthias Brugger , linux-gpio@vger.kernel.org, linux-arm Mailing List , lkml , Chuanjia Liu , Thomas Gleixner Subject: Re: [PATCH 2/2] pinctrl: mediatek: Update cur_mask in mask/mask ops To: Evan Green , Nicolas Boichat User-Agent: alot/0.8.1 Date: Mon, 10 Jun 2019 15:25:53 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Evan Green (2019-05-30 10:12:03) > On Wed, May 15, 2019 at 1:05 AM Nicolas Boichat w= rote: > > > > On Wed, May 15, 2019 at 4:14 AM Stephen Boyd wrot= e: > > > > > We could immediately unmask those lines in the hardware when the > > > set_wake() callback is called. That way the genirq layer can use the > > > driver to do what it wants with the hardware and the driver can make > > > sure that set_wake() will always cause the wakeup interrupt to be > > > delivered to genirq even when software has disabled it. > > > > > > But I think that there might be a problem with how genirq understands > > > the masked state of a line when the wakeup implementation conflates > > > masked state with wakeup armed state. Consider this call-flow: > > > > > > irq masked in hardware, IRQD_IRQ_MASKED is set > > > enable_irq_wake() > > > unmask_irq in hardware > > > IRQD_WAKEUP_ARMED is set > > > > > > handle_level_irq() > > > mask_ack_irq() > > > mask_irq() > > > if (irqd_irq_masked()) -> returns true and skips maskin= g! > > > if (desc->irq_data.chip->irq_ack) > > > ... > > > irq_may_run() > > > irq_pm_check_wakeup() > > > irq_disable() > > > mask_irq() -> does nothing again > > > > > > In the above flow, we never mask the irq because we thought it was > > > already masked when it was disabled, but the irqchip implementation > > > unmasked it to make wakeup work. Maybe we should always mask the irq = if > > > wakeup is armed and we're trying to call mask_irq()? Looks hacky. > > > > > > diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c > > > index 51128bea3846..20257d528880 100644 > > > --- a/kernel/irq/chip.c > > > +++ b/kernel/irq/chip.c > > > @@ -411,7 +411,7 @@ static inline void mask_ack_irq(struct irq_desc *= desc) > > > > > > void mask_irq(struct irq_desc *desc) > > > { > > > - if (irqd_irq_masked(&desc->irq_data)) > > > + if (!irqd_is_wakeup_armed(&desc->irq_data) && irqd_irq_masked= (&desc->irq_data)) > > > return; > > > > > > if (desc->irq_data.chip->irq_mask) { > > > > I'm... really not sure what's the best approach here. But basically, > > yes, if we can find a way to properly handle wake and interrupt > > behaviour for drivers with a single mask, that'd be good. > > IRQCHIP_MASK_ON_SUSPEND only seems to be doing half of the work, since > > it does not cover the disable+wake source case. > > > > Thanks, >=20 > I finally got around to studying this patch. This series seems okay to > me. The underlying problem is really that the hardware IRQ enabled > state is out of sync with what Linux thinks. This happens during > suspend because Linux thinks the irq is disabled, but due to the > hardware constraints on this platform, the interrupt has to be enabled > for it to be a wake source. So the mtk driver re-enables the > interrupt, and then has to find a way to get back in sync with Linux's > IRQ mask state. >=20 > One possible approach is mentioned above by Stephen: stop calling > disable_irq in the cros EC driver. Then both linux and mtk agree the > interrupt is enabled at suspend time. I think this ran into other > problems though, where the EC gets its interrupt but is unable to > silence it because the underlying SPI bus is still suspended. Does this happen? I thought the interrupt would only be delivered once all drivers have resumed from the noirq resume phase. Maybe the SPI controller needs to resume there instead of in the normal resume path and then this isn't a problem. >=20 > The other approach, taken here, is to mask the interrupt when it first > comes in, getting Linux and mtk back in agreement that yes, the > interrupt is masked. Outside of enlightening the generic IRQ core > about these types of interrupts that need to get re-enabled to be wake > sources, this seems like a reasonable approach. I prefer we teach the genirq layer about these types of irqchips. That way the solution is common and not a one-off fix for Mediatek chips. I'm sure that this same problem will come up again for another SoC vendor out there so having a chip flag that does the other half of IRQCHIP_MASK_ON_SUSPEND would be appropriate.