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([2600:1010:b062:7159:60af:2fa5:3435:5195]) by smtp.gmail.com with ESMTPSA id s42sm3106035pjc.5.2019.06.11.09.04.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 09:04:32 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v4 3/5] x86/umwait: Add sysfs interface to control umwait C0.2 state From: Andy Lutomirski X-Mailer: iPhone Mail (16F203) In-Reply-To: <20190611085410.GT3436@hirez.programming.kicks-ass.net> Date: Tue, 11 Jun 2019 09:04:30 -0700 Cc: Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Andy Lutomirski , Ashok Raj , Tony Luck , Ravi V Shankar , linux-kernel , x86 Content-Transfer-Encoding: quoted-printable Message-Id: <0D67CEAC-9710-4ECB-9248-75B48542FF82@amacapital.net> References: <1559944837-149589-1-git-send-email-fenghua.yu@intel.com> <1559944837-149589-4-git-send-email-fenghua.yu@intel.com> <20190611085410.GT3436@hirez.programming.kicks-ass.net> To: Peter Zijlstra Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Jun 11, 2019, at 1:54 AM, Peter Zijlstra wrote: >=20 >> On Fri, Jun 07, 2019 at 03:00:35PM -0700, Fenghua Yu wrote: >> C0.2 state in umwait and tpause instructions can be enabled or disabled >> on a processor through IA32_UMWAIT_CONTROL MSR register. >>=20 >> By default, C0.2 is enabled and the user wait instructions result in >> lower power consumption with slower wakeup time. >>=20 >> But in real time systems which require faster wakeup time although power >> savings could be smaller, the administrator needs to disable C0.2 and all= >> C0.2 requests from user applications revert to C0.1. >>=20 >> A sysfs interface "/sys/devices/system/cpu/umwait_control/enable_c02" is >> created to allow the administrator to control C0.2 state during run time.= >=20 > We already have an interface for applications to convey their latency > requirements (pm-qos). We do not need another magic sys variable. I=E2=80=99m not sure I agree. This isn=E2=80=99t an overall latency request= , and setting an absurdly low pm_qos will badly hurt idle power and turbo pe= rformance. Also, pm_qos isn=E2=80=99t exactly beautiful. (I speak from some experience. I may be literally the only person to write a= driver that listens to dev_pm_qos latency requests. And, in my production b= ox, I directly disable c states instead of messing with pm_qos.) I do wonder whether anyone will ever use this particular control, though.=