Received: by 2002:a25:ab43:0:0:0:0:0 with SMTP id u61csp5403457ybi; Wed, 12 Jun 2019 01:49:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqxFZ/tEMND43vqG/8Ym/eQ7HeHzEABZqyyMhou8R7niNYbPsSgqcbwlBcxfyuZZbl8lI57g X-Received: by 2002:aa7:80d2:: with SMTP id a18mr4598355pfn.152.1560329399029; Wed, 12 Jun 2019 01:49:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560329399; cv=none; d=google.com; s=arc-20160816; b=xgiSn67hu98IFAM/e3wEIQBcbOHH9F4XSStN4WrAqb82+bsAJVA8rbLr3MFP/4cMPU 9g2nPyNfzUk/Yw3IwRebniVSRsxaEnuB0dUBgHuI+8P3pKETgUiN8+F1/U/XUeigfwBH LonZEFINCQcGVu0PG3hg/QWLnPnh3hMKzeWPjXK12Jr1GjeFzPyH5ryQo1Un2BhhMJDR 50V+dZ6sLGYiO1JK0qjdqGlnh56QBTp9q43ZEuVSH5HOUOAEqRfWMCgxKyF0UgjiQhSu 1Q/1CQnk70MVwDjPDsVCJo8ldTDVyKnfwAwJbL7tQGB258H2Pd461yby78KX/n2yHdLo a2Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:date:cc:to:from:subject:message-id; bh=QBq+7GL051li67tpHWiKAQ0PdnNPj/UafAm7Mmgf+DQ=; b=Qy489dKp86ztC4pMlSEnSyI4g4Xb06i0Po3FynVBeDBxPy1ISSlrivNp7inWxDUesT WokNlpIs9ozK7jq+BTeDdygB3qRO6Dwh8ZjIFNatYy1zKW5S/1AwQs9iwyNLGJp8o2I8 3+0mrD+YKSVAOcYLBRS43U/THYsPb1DwmqbQs7o6W4nROF8PBtuljxUrEWwDWF1VCzCM 3RZ4P3MyggCV/iaNWDRFQi1cpFLa2ECVoposILvVK84HX8he+xLl2mUNKJsn+iv/CmXI 1C9QC553yZsLOzY3MPYJQBmcZFz5Y1OLk7bzT9XDP7f6bcMawjsVMDBRNsASEKRmn4nP a7rQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 97si15058624plc.181.2019.06.12.01.49.44; Wed, 12 Jun 2019 01:49:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2407634AbfFLISH (ORCPT + 99 others); Wed, 12 Jun 2019 04:18:07 -0400 Received: from gate.crashing.org ([63.228.1.57]:33427 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726609AbfFLISG (ORCPT ); Wed, 12 Jun 2019 04:18:06 -0400 Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id x5C8HkA7008611; Wed, 12 Jun 2019 03:17:47 -0500 Message-ID: Subject: Re: [PATCH v2 8/8] habanalabs: enable 64-bit DMA mask in POWER9 From: Benjamin Herrenschmidt To: "Oliver O'Halloran" Cc: Oded Gabbay , Greg KH , linuxppc-dev@ozlabs.org, Christoph Hellwig , Russell Currey , "Linux-Kernel@Vger. Kernel. Org" Date: Wed, 12 Jun 2019 18:17:46 +1000 In-Reply-To: References: <20190611092144.11194-1-oded.gabbay@gmail.com> <20190611095857.GB24058@kroah.com> <20190611151753.GA11404@infradead.org> <20190611152655.GA3972@kroah.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2019-06-12 at 15:45 +1000, Oliver O'Halloran wrote: > > Also, are you sure about the MSI thing? The IODA3 spec says the only > important bits for a 64bit MSI are bits 61:60 (to hit the window) and > the lower bits that determine what IVE to use. Everything in between > is ignored so ORing in bit 59 shouldn't break anything. On IODA3... could be different on another system. My point is you can't just have a fixed setting for all top bits for DMA & MSIs. > > This will only work as long as all of the system memory can be > > addressed at an offset from that fixed address that itself fits your > > device addressing capabilities (50 bits in this case). It may or may > > not be the case but there's no way to check since the DMA mask logic > > won't really apply. > > > > You might want to consider fixing your HW in the next iteration... This > > is going to bite you when x86 increases the max physical memory for > > example, or on other architectures. > > Yes, do this. The easiest way to avoid this sort of wierd hack is to > just design the PCIe interface to the spec in the first place. Ben.