Received: by 2002:a25:ab43:0:0:0:0:0 with SMTP id u61csp5460479ybi; Wed, 12 Jun 2019 02:55:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzwk2724HmfypZwB9kx2cdYKXAdpvXpHlqNHc6di2sc+J4Qx7L1f7T7NMTHRDTy2imG44Kj X-Received: by 2002:a65:668e:: with SMTP id b14mr20307308pgw.407.1560333342727; Wed, 12 Jun 2019 02:55:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560333342; cv=none; d=google.com; s=arc-20160816; b=i74WpaeJbqoVMsGXeILKijs1TvcvC9tp+pdeQTNsAErhC3IUWN+AFUkTFXyK6ObJrG wqyB6htBXebvC+sZzBo3Gwqc2WL+QvXRLfL80P3YFnWSjwGbgsRro0gig0dDktLJauNY 3H3JC4a1rV7dr/Qgh+fShOMpcTa7Z0sIod6+ZRIHRv+tgGWH6EIM0N4sQmm+4s2PZmIS lLDtymV2p75JlBr/DoalZFPymv52BcVfg201G0UO2zkrbFus9g7ZaOaUBUNN90T7tkUy NKv75UkvdlTXT/HjPte8HRjha/88XZv1VB5QNyVio/3YCaybDkTj1MKTjarBaOAwDUsJ /rzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=FiwNfww156FiifgKif7x2Opb0H6CxjyTvjusYAyc3Kc=; b=JCwZ/1iRHi5kUxwIX9/E2+tif8rgYnA6VNQsylRlMO9Hu/7OvwPw+NNIH4bplsuGCE ItonpJWILnxMs93jVxjmw8i4g3y7LqC4Yw/AyJEzi9p85k/iLpanSur3R/OZ26Kg34d1 T8kFnHkNxy2x3zda4Rr8xGt5omHf7dWxCZzpAlv13plSNMB15S/jDX2OGpFd0KM3UPio l743NU7JsBjITNmTtQwT/f2cGf+FmX4LH07EYuaBCb2lk8o1nvQs3B49/mEpVb6jVR1g tm23ClSJ/jFR/3Y72Q+2uT8DUvJR6qOutEMWlP9sG2P9mVeu6IR7f0Y+7bIELcpUs13l tSYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=nA9YlpAw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j66si15406755plb.375.2019.06.12.02.55.27; Wed, 12 Jun 2019 02:55:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=nA9YlpAw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437864AbfFLJy6 (ORCPT + 99 others); Wed, 12 Jun 2019 05:54:58 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17655 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2437696AbfFLJy6 (ORCPT ); Wed, 12 Jun 2019 05:54:58 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 12 Jun 2019 02:54:54 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 12 Jun 2019 02:54:57 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 12 Jun 2019 02:54:57 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 12 Jun 2019 09:54:56 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 12 Jun 2019 09:54:56 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 12 Jun 2019 02:54:56 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V10 07/15] PCI: dwc: Add support to enable CDM register check Date: Wed, 12 Jun 2019 15:23:31 +0530 Message-ID: <20190612095339.20118-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190612095339.20118-1-vidyas@nvidia.com> References: <20190612095339.20118-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560333294; bh=FiwNfww156FiifgKif7x2Opb0H6CxjyTvjusYAyc3Kc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=nA9YlpAwG6NW+vbaZJ7sCR7jf5jrDG/Clt9c0JauIFaZ1jsqtg5eiiLiPE70tr4tC li+IK8JaYaQph6wZMkGvSW/k3qxlbf2mmioVdxKLtorZZEcO6T4eC0djcEO7jT9KJx 5dOzYDjm5eyZ+Hw6GvijZlt6l8mCohcRrWkhK/rJf9VRSDFo7p5LfHZk1g9+4NFAFe IE3AdnPsCwQz06CEbz1FhW/wWfFIV2AtYGw2sG0FHUx09BiSxfk0M3NbztRFwguCKl LIy1ntDjXMqzZKx3bBgfqX8/0VIOpFBfHYbMsi2VeG4X6bStilFRTDHfFXTsr8gWOe lGLaHQi8owGtA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support to enable CDM (Configuration Dependent Module) register check for any data corruption based on the device-tree flag 'snps,enable-cdm-check'. Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel Reviewed-by: Thierry Reding --- Changes since [v9]: * None Changes since [v8]: * None Changes since [v7]: * None Changes since [v6]: * Changed "enable-cdm-check" to "snps,enable-cdm-check" Changes since [v5]: * None Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * Changed code and commit description to reflect change in flag from 'cdm-check' to 'enable-cdm-check' Changes since [v1]: * This is a new patch in v2 series drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d8be6c3339fa..e9a059163034 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -521,4 +521,11 @@ void dw_pcie_setup(struct dw_pcie *pci) break; } dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + if (of_property_read_bool(np, "snps,enable-cdm-check")) { + val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); + val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | + PCIE_PL_CHK_REG_CHK_REG_START; + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 45cd7c88d28a..6f555025caf9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -86,6 +86,15 @@ #define PCIE_MISC_CONTROL_1_OFF 0x8BC #define PCIE_DBI_RO_WR_EN BIT(0) +#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 +#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) +#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) +#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16) +#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17) +#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18) + +#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 + /* * iATU Unroll-specific register definitions * From 4.80 core version the address translation will be made by unroll -- 2.17.1