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[209.132.180.67]) by mx.google.com with ESMTP id i123si279835pfc.60.2019.06.12.09.53.45; Wed, 12 Jun 2019 09:54:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730643AbfFLLWz (ORCPT + 99 others); Wed, 12 Jun 2019 07:22:55 -0400 Received: from foss.arm.com ([217.140.110.172]:50900 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725771AbfFLLWy (ORCPT ); Wed, 12 Jun 2019 07:22:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C88FA28; Wed, 12 Jun 2019 04:22:53 -0700 (PDT) Received: from big-swifty.misterjones.org (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 262D93F246; Wed, 12 Jun 2019 04:24:30 -0700 (PDT) Date: Wed, 12 Jun 2019 12:22:41 +0100 Message-ID: <868su7gi9q.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Lorenzo Pieralisi , "Z.q. Hou" Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Xiaowei Bao , "linux-pci@vger.kernel.org" , "l.subrahmanya@mobiveil.co.in" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI In-Reply-To: <3b883516-1d63-1504-bdc9-22ac9c6f2d46@arm.com> References: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> <20190412083635.33626-5-Zhiqiang.Hou@nxp.com> <20190611165935.GA22836@redmoon> <3b883516-1d63-1504-bdc9-22ac9c6f2d46@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 11 Jun 2019 18:29:49 +0100, Marc Zyngier wrote: > > On 11/06/2019 17:59, Lorenzo Pieralisi wrote: > > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote: > >> From: Hou Zhiqiang > >> > >> The current code does not support multiple MSIs, so remove > >> the corresponding flag from the msi_domain_info structure. > > > > Please explain me what's the problem before removing multi MSI > > support. > > The reason seems to be the following code in the allocator: > > WARN_ON(nr_irqs != 1); > mutex_lock(&msi->lock); > > bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); > if (bit >= msi->num_of_vectors) { > mutex_unlock(&msi->lock); > return -ENOSPC; > } > > set_bit(bit, msi->msi_irq_in_use); > > So instead of fixing the allocator, the author prefers disabling > the feature. I'm not sure whether that is an acceptable outcome... Actually, there is a much deeper issue, and the compose_msi_msg callback gives a clue: phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); This thing is using a separate target address per MSI, which is the killer argument. Bad hardware... Thanks, M. -- Jazz is not dead, it just smells funny.