Received: by 2002:a25:ab43:0:0:0:0:0 with SMTP id u61csp5932942ybi;
        Wed, 12 Jun 2019 10:57:14 -0700 (PDT)
X-Google-Smtp-Source: APXvYqzOs0hbOIskP7JSC25LDYTJoTsb4N3+nVVMajNeq4w9YDMyrlZcjKx5dp99MPQ7g4nbzsZr
X-Received: by 2002:a17:90a:65c2:: with SMTP id i2mr440083pjs.54.1560362234299;
        Wed, 12 Jun 2019 10:57:14 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1560362234; cv=none;
        d=google.com; s=arc-20160816;
        b=ISLIZkWRbyRr4iVluCiEvQSuWrHZ1Mvn4toPZFXxHa3ttbLLXmk0BTo8AST5f79ZTd
         VUY1YM82kXSuHAeiOIbTmL44JC7CiDSA9c/fsAHA4zbP4PDCmT5L3BoCiU/RRzBpwKOh
         qC26wbPXYe8Q78eOIvTfHv86DiS+q7VLmtx60WJ7LmyE74i3xPH5kBxt3hkYgv7dfsna
         E15vPZmn6ZujIaXbhO+iYv8fhk3VYCI5PnbendRxVQp2sZ7/W6e8v83SylJ11jBpnbz2
         3EkxjPefqV2f2cZ8HlsS0ry0UrUfuzIqEC51Uf644ccvPzW0HInr7T5CGJ+wM7KAQwD0
         nmEg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:content-language
         :content-transfer-encoding:in-reply-to:mime-version:user-agent:date
         :message-id:from:references:cc:to:subject;
        bh=PxIsfwb57+HaLFo01hW98b87Q1GeaYcpfwvv//9lWUQ=;
        b=fD5s2M0DDA+NKiN83WjUHLVmcbWCF9c7WsrpHZbw5FAMlYxgICW2wmJcdy5F0BywmK
         kCnlKnqsqjZXfIBWl1CDuD0peHvInqJSDZVpnTCOzQEFC0YWIS5RrKGlJha/ORGmPoZk
         3dEAxW68GHNOTrIrCBTA3ZgtKLHyAxD+Wj5g9n8w4hTGFc4SO8RRiCWqgIQW+Dnc5Alj
         D763hv8oFT+D6+cQfTByrDoxMkW+6LwcctVCzPlKT/fiX28FFeaFriLsRkh9wrHcSGYD
         X6+NOp74RHBXKZLjMFMzJze4qeBvQ+47RjUjAKCqCQ8bi4qwD8XPaRFTCQyXUja/Y3QH
         +x0Q==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b="MERg7/4w";
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id s1si433803pjb.23.2019.06.12.10.56.59;
        Wed, 12 Jun 2019 10:57:14 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b="MERg7/4w";
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S2439337AbfFLM7Z (ORCPT <rfc822;fezhang.suse@gmail.com>
        + 99 others); Wed, 12 Jun 2019 08:59:25 -0400
Received: from hqemgate16.nvidia.com ([216.228.121.65]:11483 "EHLO
        hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1727783AbfFLM7Z (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Wed, 12 Jun 2019 08:59:25 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5d00f72c0000>; Wed, 12 Jun 2019 05:59:24 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Wed, 12 Jun 2019 05:59:24 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Wed, 12 Jun 2019 05:59:24 -0700
Received: from [10.25.72.203] (172.20.13.39) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 12 Jun
 2019 12:59:20 +0000
Subject: Re: [PATCH v2 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
To:     Jon Hunter <jonathanh@nvidia.com>, <thierry.reding@gmail.com>,
        <robh+dt@kernel.org>, <mark.rutland@arm.com>
CC:     <mkumard@nvidia.com>, <devicetree@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <1560243406-2535-1-git-send-email-spujar@nvidia.com>
 <1f2020ae-12f3-2ad1-c844-b4b7885d41f9@nvidia.com>
From:   Sameer Pujar <spujar@nvidia.com>
Message-ID: <ad169cb8-733c-96d4-5eee-1131c53320b6@nvidia.com>
Date:   Wed, 12 Jun 2019 18:29:17 +0530
User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101
 Thunderbird/60.7.0
MIME-Version: 1.0
In-Reply-To: <1f2020ae-12f3-2ad1-c844-b4b7885d41f9@nvidia.com>
X-Originating-IP: [172.20.13.39]
X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To
 HQMAIL107.nvidia.com (172.20.187.13)
Content-Type: text/plain; charset="utf-8"; format=flowed
Content-Transfer-Encoding: 7bit
Content-Language: en-GB
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1560344364; bh=PxIsfwb57+HaLFo01hW98b87Q1GeaYcpfwvv//9lWUQ=;
        h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date:
         User-Agent:MIME-Version:In-Reply-To:X-Originating-IP:
         X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding:
         Content-Language;
        b=MERg7/4wgAxVM9YsKDXA3sGLIGuPSWq9Y5tF3OIQNvV8nw51zq/K2Xx8zNybi3h4U
         9d2gYLJvtpsZ8opwHysCdUqaTq01CtjluPLCz/mqHebmSMtQM5sSBZN/iKzvVmN0++
         MgJGdcruFhIKqOngNye4NVOfz1vCfhW8RSnUdur/41q1Z5Yo1gdDkZ33DvWWu2Qc3R
         yC0mFlwjELvG4VorYWkIgrX/nL3FOuAhZ1PZyltPM46HREQZLsD9aCGBDVZxmjfNPU
         iAQiAsmebzYPny5G26uGTddXYFj19qfUKEoQcpfikI6l6zyhIdIsa8JBwJohv3Z1gU
         Pz6Ely34dTK+Q==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 6/12/2019 6:06 PM, Jon Hunter wrote:
> On 11/06/2019 09:56, Sameer Pujar wrote:
>> Add DT nodes for following devices on Tegra186 and Tegra194
>>   * ACONNECT
>>   * ADMA
>>   * AGIC
>>
>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>> ---
>>   arch/arm64/boot/dts/nvidia/tegra186.dtsi | 68 ++++++++++++++++++++++++++++++++
>>   arch/arm64/boot/dts/nvidia/tegra194.dtsi | 68 ++++++++++++++++++++++++++++++++
>>   2 files changed, 136 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> index 426ac0b..ccd902b 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> @@ -1295,4 +1295,72 @@
>>   				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>   		interrupt-parent = <&gic>;
>>   	};
>> +
>> +	aconnect@2a41000 {
>> +		compatible = "nvidia,tegra210-aconnect";
>> +		clocks = <&bpmp TEGRA186_CLK_APE>,
>> +			 <&bpmp TEGRA186_CLK_APB2APE>;
>> +		clock-names = "ape", "apb2ape";
>> +		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0x02930000 0x0 0x02930000 0x50000
>> +			  0x02a41000 0x0 0x02a41000 0x3000>;
> We only need one address range here that covers the entire APE.
will update.
>
>> +		status = "disabled";
>> +
>> +		dma-controller@2930000 {
>> +			compatible = "nvidia,tegra186-adma";
>> +			reg = <0x02930000 0x50000>;
>> +			interrupt-parent = <&agic>;
>> +			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> +			#dma-cells = <1>;
>> +			clocks = <&bpmp TEGRA186_CLK_AHUB>;
>> +			clock-names = "d_audio";
>> +			status = "disabled";
>> +		};
>> +
>> +		agic: agic@2a41000 {
>> +			compatible = "nvidia,tegra210-agic";
>> +			#interrupt-cells = <3>;
>> +			interrupt-controller;
>> +			reg = <0x02a41000 0x1000>,
>> +			      <0x02a41000 0x2000>;
> These addresses should not overlap.
typo! will fix, Thanks.
>
> Cheers
> Jon
>