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Subject: Re: [PATCH v2 3/6] clocksource/drivers/tegra: Set and use timer's
 period
To:     Dmitry Osipenko <digetx@gmail.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Joseph Lo <josephl@nvidia.com>,
        Thierry Reding <thierry.reding@gmail.com>,
        Peter De Schrijver <pdeschrijver@nvidia.com>
CC:     <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20190610164400.11830-1-digetx@gmail.com>
 <20190610164400.11830-4-digetx@gmail.com>
 <ac8a1da8-9b82-3d5a-5fa6-0c1cc7f627f1@nvidia.com>
 <3e941c50-ac62-719e-aac1-7072e9a3bcd0@gmail.com>
From:   Jon Hunter <jonathanh@nvidia.com>
Message-ID: <660f3645-3fa6-175c-75a6-3fcc79e972ad@nvidia.com>
Date:   Mon, 17 Jun 2019 11:51:43 +0100
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On 14/06/2019 17:45, Dmitry Osipenko wrote:
> 14.06.2019 18:48, Jon Hunter =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>>
>> On 10/06/2019 17:43, Dmitry Osipenko wrote:
>>> The of_clk structure has a period field that is set up initially by
>>> timer_of_clk_init(), that period value need to be adjusted for a case o=
f
>>> TIMER1-9 that are running at a fixed rate that doesn't match the clock'=
s
>>> rate. Note that the period value is currently used only by some of the
>>> clocksource drivers internally and hence this is just a minor cleanup
>>> change that doesn't fix anything.
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>> ---
>>>  drivers/clocksource/timer-tegra.c | 5 +++--
>>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/ti=
mer-tegra.c
>>> index 810b4e7435cf..646b3530c2d2 100644
>>> --- a/drivers/clocksource/timer-tegra.c
>>> +++ b/drivers/clocksource/timer-tegra.c
>>> @@ -71,9 +71,9 @@ static int tegra_timer_shutdown(struct clock_event_de=
vice *evt)
>>>  static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>>  {
>>>  	void __iomem *reg_base =3D timer_of_base(to_timer_of(evt));
>>> +	unsigned long period =3D timer_of_period(to_timer_of(evt));
>>> =20
>>> -	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
>>> -		       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>>> +	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
>>>  		       reg_base + TIMER_PTV);
>>> =20
>>>  	return 0;
>>> @@ -297,6 +297,7 @@ static int __init tegra_init_timer(struct device_no=
de *np, bool tegra20,
>>>  		cpu_to->clkevt.rating =3D rating;
>>>  		cpu_to->clkevt.cpumask =3D cpumask_of(cpu);
>>>  		cpu_to->of_base.base =3D timer_reg_base + base;
>>> +		cpu_to->of_clk.period =3D DIV_ROUND_UP(rate, HZ);
>>
>> Any reason you made this a round-up?
>=20
> That's what timer_of_clk_init() does, I assume it should be a more correc=
t variant.

Sounds to me like this should be 2 patches, because you are changing the
value. This is not just purely cleanup IMO.

Jon

--=20
nvpublic