Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <20190611185102.368ED21744@mail.kernel.org> <671f87d6-f4a4-6d2c-967b-e1aa0677d83e@codeaurora.org>
 <b0fdbcb1-4d5d-5c60-4150-7762a577cd10@codeaurora.org>
In-Reply-To: <b0fdbcb1-4d5d-5c60-4150-7762a577cd10@codeaurora.org>
From:   Linus Walleij <linus.walleij@linaro.org>
Date:   Mon, 17 Jun 2019 13:50:09 +0200
Message-ID: <CACRpkdahUNNOhQdri3T86jHr+qOBmXH61_AMmoWpv_be2koMrw@mail.gmail.com>
Subject: Re: Fwd: Re: [PATCH] pinctrl: qcom: Clear status bit on irq_unmask
To:     Neeraj Upadhyay <neeraju@codeaurora.org>,
        Hans Verkuil <hverkuil@xs4all.nl>
Cc:     Stephen Boyd <sboyd@kernel.org>,
        Tengfei Fan <tengfeif@codeaurora.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        MSM <linux-arm-msm@vger.kernel.org>, sramana@codeaurora.org
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Mon, Jun 17, 2019 at 12:35 PM Neeraj Upadhyay <neeraju@codeaurora.org> wrote:

> Hi Stephen, there is one use case with is not covered by commit
> b55326dc969e (
>
> "pinctrl: msm: Really mask level interrupts to prevent latching"). That
> happens when
>
> gpio line is toggled between i/o mode and interrupt mode :
>
> 1. GPIO is configured as irq line. Peripheral raises interrupt.
>
> 2. IRQ handler runs and disables the irq line (through wq work).
>
> 3. GPIO is configured for input and and data is received from the
> peripheral.

There is no distinction between using a GPIO line as input
and using it for IRQ. All input GPIOs can be used for IRQs,
if the hardware supports it (has an irqchip).

> 4. Now, when GPIO is re-enabled as irq, we see spurious irq, and there
> isn't
>
> any data received on the gpio line, when it is read back after
> configuring as input.

That's an interesting usecase. Hans Verkuil reworked the
GPIO irq support very elegantly exactly to support this type
of usecase (irq switch on and off dynamically), where he
was even switching the line into output mode between
the IRQ trains. (one-wire transcactions for CEC).

> Patch https://lkml.org/lkml/2019/6/17/226 tries to cover this use case.
> Can you please provide your comments?

What this patch does is clear all pending IRQs at irq
unmask. This is usually safe, unless there may be cases
where you *want* to catch any pending IRQs. I guess
normally you don't so it should be safe?

The corner case is when you start some transaction
or whatever that gets ACKed by an IRQ and you actually
get the IRQ back before you had time to execute the code
enabling the IRQ.

That would be racy and bad code, as you should clearly
enable the IRQ first, then start the transaction. So I think
this patch is safe.

But let's see what Bjorn says.

Yours,
Linus Walleij