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[209.132.180.67]) by mx.google.com with ESMTP id w4si10378154pgr.150.2019.06.17.08.15.21; Mon, 17 Jun 2019 08:15:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=UEnJRIvQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728281AbfFQPPA (ORCPT + 99 others); Mon, 17 Jun 2019 11:15:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:45616 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727670AbfFQPPA (ORCPT ); Mon, 17 Jun 2019 11:15:00 -0400 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3F8522166E for ; Mon, 17 Jun 2019 15:14:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560784499; bh=b1+p3mYa5dcNTWiscCTfox6sPzLm0XFFNEeLduQHIzc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=UEnJRIvQrSzZK1hbeKKJPljnWI19XRtBxLD4asFVxhyPBmZL4ZO0dRJZUpR/xlHOj sQ769iEQPPX7MqxWPdj66bkFn6GA4Kv9Oabba64HecEYnP/2SouFzlp++8Oj88XwUA v0gwZQppcg5h1B+Nk3LQhQxYiTOgjF8yPAupMIPA= Received: by mail-wr1-f49.google.com with SMTP id k11so10412432wrl.1 for ; Mon, 17 Jun 2019 08:14:59 -0700 (PDT) X-Gm-Message-State: APjAAAWkdFMmB6cwwycJPaQr8WaavOoFAuMJLsfxeBXYmT5kWzdYyLoI nMbgOZtfPWQr1u/c6RHoZzk6HSuiUd0jzk6kgOLj4Q== X-Received: by 2002:a5d:6a42:: with SMTP id t2mr12160574wrw.352.1560784497814; Mon, 17 Jun 2019 08:14:57 -0700 (PDT) MIME-Version: 1.0 References: <1559944837-149589-1-git-send-email-fenghua.yu@intel.com> <1559944837-149589-4-git-send-email-fenghua.yu@intel.com> <20190611085410.GT3436@hirez.programming.kicks-ass.net> <0D67CEAC-9710-4ECB-9248-75B48542FF82@amacapital.net> <20190611172717.GC3436@hirez.programming.kicks-ass.net> In-Reply-To: <20190611172717.GC3436@hirez.programming.kicks-ass.net> From: Andy Lutomirski Date: Mon, 17 Jun 2019 08:14:44 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/5] x86/umwait: Add sysfs interface to control umwait C0.2 state To: Peter Zijlstra Cc: Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Andy Lutomirski , Ashok Raj , Tony Luck , Ravi V Shankar , linux-kernel , x86 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 11, 2019 at 10:27 AM Peter Zijlstra wrot= e: > > > (can you, perchance, look at a MUA that isn't 'broken' ?) > > On Tue, Jun 11, 2019 at 09:04:30AM -0700, Andy Lutomirski wrote: > > > > > > > On Jun 11, 2019, at 1:54 AM, Peter Zijlstra wr= ote: > > > > > >> On Fri, Jun 07, 2019 at 03:00:35PM -0700, Fenghua Yu wrote: > > >> C0.2 state in umwait and tpause instructions can be enabled or disab= led > > >> on a processor through IA32_UMWAIT_CONTROL MSR register. > > >> > > >> By default, C0.2 is enabled and the user wait instructions result in > > >> lower power consumption with slower wakeup time. > > >> > > >> But in real time systems which require faster wakeup time although p= ower > > >> savings could be smaller, the administrator needs to disable C0.2 an= d all > > >> C0.2 requests from user applications revert to C0.1. > > >> > > >> A sysfs interface "/sys/devices/system/cpu/umwait_control/enable_c02= " is > > >> created to allow the administrator to control C0.2 state during run = time. > > > > > > We already have an interface for applications to convey their latency > > > requirements (pm-qos). We do not need another magic sys variable. > > > > I=E2=80=99m not sure I agree. This isn=E2=80=99t an overall latency re= quest, and > > setting an absurdly low pm_qos will badly hurt idle power and turbo > > performance. Also, pm_qos isn=E2=80=99t exactly beautiful. > > > > (I speak from some experience. I may be literally the only person to > > write a driver that listens to dev_pm_qos latency requests. And, in my > > production box, I directly disable c states instead of messing with > > pm_qos.) > > > > I do wonder whether anyone will ever use this particular control, thoug= h. > > I agree that pm-qos is pretty terrible; but that doesn't mean we should > just add random control files all over the place. I don't think pm-qos is expressive enough. It seems entirely reasonable to want to do a C0.1 wait for lower latency *while waiting* but still want full power-saving idle when not waiting. Do we even know what the C0.2 and C0.1 latencies are? And why is this thing an MSR instead of a flag passed to UMWAIT? --Andy