Received: by 2002:a25:ab43:0:0:0:0:0 with SMTP id u61csp4273875ybi; Tue, 18 Jun 2019 15:10:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhP4NUYzCKzA5sKE5f4pfWzpwxse2vu1fWCJd3LQy1Ceia/5tK3By+dZKKBRMElZ3AhulK X-Received: by 2002:aa7:8b17:: with SMTP id f23mr87500439pfd.194.1560895856934; Tue, 18 Jun 2019 15:10:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560895856; cv=none; d=google.com; s=arc-20160816; b=ohEILXFkbW05Gtk9zFx24OT/kbOtXdsalbquMIRwFG29mSMZ6fEzO6A6+mm0h6Itrv 4PUcR7cTxUef9poXAjrbM7NlAJCDTSGmtKUHUuo0lRPf3AQyyev16eHiXVV3w5g7otpw 6zZTm+r9zDjZgqmcisVMDCbFsFN4iG3KYWs0ICJtH7K6YvHDEkDxkQMzvbpvfC/r+T/C 7m/jzjF9e1s+OJaK8hBFS32TSBiC8gSW0z6mHQmxtDxwmyPWS8uy3nRvqXbcAtzTJmnJ 6LcGEmBw9uVfQzFaoBgzcbJG15z2EY2/ElTC3Mlb/ChdaE2N+e/vWshoFGVA97dbZKri 2bSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:organization:references:in-reply-to:date:cc:to:from :subject:message-id; bh=5srDh8FwBaROXbZgb7TmRZ0rRqNS49Asi4YcIWYrnio=; b=AZTZP7E4/7HxkhoBqmabmLveARjilTRHUqyZJwUKMc+rqADYRFFZdoAjoUsezxaMSj xCd71uM5SYEmMSRL6Yc56SDMy6JosTMLoRtdLEKrweE97PWTp84tjtN8qvW1CsDChkJT LROaOaj+OJbLFJFMqq37E2tAVkgBeYuVQIkZdO0VLX5QRnFriuC/MpkZ6hBgRNHvbcp/ 3L7PuLcqCrkfBATqBEwnrqtgmmY1fDDDeE0ttdeE4ctosTWg0xs0GlQ3hUiPcr0kbVEL uDyVhMCqfld2vfjlRPQHfcfiF73iMV5iVkJ4nNWOzUkWnz/o3hytfvTTJX7TkBXgh8I9 3+Zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x21si1197248pgh.400.2019.06.18.15.10.30; Tue, 18 Jun 2019 15:10:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730766AbfFRWKK (ORCPT + 99 others); Tue, 18 Jun 2019 18:10:10 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:35970 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729982AbfFRWKK (ORCPT ); Tue, 18 Jun 2019 18:10:10 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id 8027C260D74 Message-ID: <20372cd5e56d67b8e896c2d94b3d0d136cc2886e.camel@collabora.com> Subject: Re: [PATCH 2/3] drm/rockchip: Add optional support for CRTC gamma LUT From: Ezequiel Garcia To: Ilia Mirkin Cc: dri-devel , linux-rockchip@lists.infradead.org, Heiko =?ISO-8859-1?Q?St=FCbner?= , Sandy Huang , kernel@collabora.com, Sean Paul , Boris Brezillon , Douglas Anderson , Jacopo Mondi , Rob Herring , Mark Rutland , devicetree , LKML Date: Tue, 18 Jun 2019 19:09:57 -0300 In-Reply-To: References: <20190618213406.7667-1-ezequiel@collabora.com> <20190618213406.7667-3-ezequiel@collabora.com> Organization: Collabora Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2019-06-18 at 17:47 -0400, Ilia Mirkin wrote: > On Tue, Jun 18, 2019 at 5:43 PM Ezequiel Garcia wrote: > > Add an optional CRTC gamma LUT support, and enable it on RK3288. > > This is currently enabled via a separate address resource, > > which needs to be specified in the devicetree. > > > > The address resource is required because on some SoCs, such as > > RK3288, the LUT address is after the MMU address, and the latter > > is supported by a different driver. This prevents the DRM driver > > from requesting an entire register space. > > > > The current implementation works for RGB 10-bit tables, as that > > is what seems to work on RK3288. > > > > Signed-off-by: Ezequiel Garcia > > --- > > Changes from RFC: > > * Request (an optional) address resource for the LUT. > > * Drop support for RK3399, which doesn't seem to work > > out of the box and needs more research. > > * Support pass-thru setting when GAMMA_LUT is NULL. > > * Add a check for the gamma size, as suggested by Ilia. > > * Move gamma setting to atomic_commit_tail, as pointed > > out by Jacopo/Laurent, is the correct way. > > --- > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > > index 12ed5265a90b..5b6edbe2673f 100644 > > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > > +static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, > > + struct drm_crtc_state *old_state) > > +{ > > + int idle, ret, i; > > + > > + spin_lock(&vop->reg_lock); > > + VOP_REG_SET(vop, common, dsp_lut_en, 0); > > + vop_cfg_done(vop); > > + spin_unlock(&vop->reg_lock); > > + > > + ret = readx_poll_timeout(vop_dsp_lut_is_enable, vop, > > + idle, !idle, 5, 30 * 1000); > > + if (ret) > > + return; > > + > > + spin_lock(&vop->reg_lock); > > + > > + if (crtc->state->gamma_lut) { > > + if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != > > + old_state->gamma_lut->base.id)) > > + vop_crtc_write_gamma_lut(vop, crtc); > > + } else { > > + for (i = 0; i < crtc->gamma_size; i++) { > > + u32 word; > > + > > + word = (i << 20) | (i << 10) | i; > > + writel(word, vop->lut_regs + i * 4); > > + } > > Note - I'm not in any way familiar with the hardware, so take with a > grain of salt -- > > Could you just leave dsp_lut_en turned off in this case? > That was the first thing I tried :-) It seems dsp_lut_en is not to enable the CRTC gamma LUT stage, but to enable writing the gamma LUT to the internal RAM. And the specs list no register to enable/disable the gamma LUT. Thanks! Eze