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[209.132.180.67]) by mx.google.com with ESMTP id b6si16973844pfa.36.2019.06.19.12.18.17; Wed, 19 Jun 2019 12:18:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=s5SZWkMj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730162AbfFSTQz (ORCPT + 99 others); Wed, 19 Jun 2019 15:16:55 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:33688 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726380AbfFSTQy (ORCPT ); Wed, 19 Jun 2019 15:16:54 -0400 Received: by mail-ed1-f65.google.com with SMTP id i11so926842edq.0; Wed, 19 Jun 2019 12:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=FBqq0iblXtu1oHyc7tuPgRLTw80COLgao0LSbxaVLpA=; b=s5SZWkMjUVanP6xaEW7UHQB5lIOnZX4QkhRWa6LtBUt8xEHuoU0U9h25jR4DeKZxsA Q+Y3QHEqF66L1Tz3pgY6SKJv6fk/3CvY3bQP00KZcspZe4ey6/Q91v25UEw4qeBjTM4D mxhiceOyd207OYbMmoI4tcuqdppbs7m+PDdFKlDU4BJFQk7mD/QposPbUzZYSBfMM/ZT CSHKhFX7+SBWNrB32ZmLEngTwyH4NOY++OU2SRcPlb3LTDxXehGcMUnyxtZ1RLdMSg3u zxf9iWDgXJZfwxhHWqRFevJbC+EWZCulOkl8vgeO2DR4IKusL1nQsejdjw02RGhuCA3H PrjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=FBqq0iblXtu1oHyc7tuPgRLTw80COLgao0LSbxaVLpA=; b=Z0aG/POWgacybg8y8lQMUkydiIL/UnfqKIABTd1RDhvAJTvkR2fJNcqXEzOupTDpC/ H4LzjZoMau3euPVAjg5bg10sgKzDZ3Eib+PZ0aSwZ5pjCXJfod1rhu/jm/4y552FolQO eyZIzWi5WrqSMNOs3VY8tU+O3nz3bTQiXtep5LCYDnGeYFbl/ewqAZr3YXikbLZChZw6 qFn9KXChCtzRSCZTcuaqSY7QMc2lLHADkO5S7ttHI9GcrXHromuxrUijZcWZ1+eCYXUn y3wyLJMWne0tlGvQ0pFXaRiQzdnAGBSjQnyH2rrgMDggvv8sx0XCTkYVUtzGNIaxfGGR 8DUw== X-Gm-Message-State: APjAAAV8AuymAHqsWqT79hntbgiKduVfDaWdmuGXoeCYJ6fxngFMGcEu EFf42spQyUHg935FYNwd0CE= X-Received: by 2002:a17:906:2191:: with SMTP id 17mr1396151eju.280.1560971812710; Wed, 19 Jun 2019 12:16:52 -0700 (PDT) Received: from archlinux-epyc ([2a01:4f9:2b:2b15::2]) by smtp.gmail.com with ESMTPSA id p3sm6161325eda.43.2019.06.19.12.16.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 19 Jun 2019 12:16:52 -0700 (PDT) Date: Wed, 19 Jun 2019 12:16:50 -0700 From: Nathan Chancellor To: Sean Paul Cc: Rob Clark , linux-arm-msm , dri-devel , freedreno@lists.freedesktop.org, LKML , clang-built-linux@googlegroups.com, kbuild test robot , Jeffrey Hugo Subject: Re: [PATCH] drm/msm/dsi: Add parentheses to quirks check in dsi_phy_hw_v3_0_lane_settings Message-ID: <20190619191650.GA25726@archlinux-epyc> References: <20190619161913.102998-1-natechancellor@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 19, 2019 at 03:13:40PM -0400, Sean Paul wrote: > On Wed, Jun 19, 2019 at 12:19 PM Nathan Chancellor > wrote: > > > > Clang warns: > > > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: warning: logical not is > > only applied to the left hand side of this bitwise operator > > [-Wlogical-not-parentheses] > > if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { > > ^ ~ > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: note: add parentheses > > after the '!' to evaluate the bitwise operator first > > if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { > > ^ > > ( ) > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: note: add parentheses > > around left hand side expression to silence this warning > > if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { > > ^ > > ( ) > > 1 warning generated. > > > > Add parentheses around the bitwise AND so it is evaluated first then > > negated. > > > > Fixes: 3dbbf8f09e83 ("drm/msm/dsi: Add old timings quirk for 10nm phy") > > Link: https://github.com/ClangBuiltLinux/linux/547 > > This link is broken, could you please fix it up? Thanks for catching this, v2 on the way. Cheers, Nathan > > The rest is: > Reviewed-by: Sean Paul > > > > > Reported-by: kbuild test robot > > Reviewed-by: Jeffrey Hugo > > Signed-off-by: Nathan Chancellor > > --- > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > > index eb28937f4b34..47403d4f2d28 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > > @@ -77,7 +77,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) > > tx_dctrl[i]); > > } > > > > - if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { > > + if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) { > > /* Toggle BIT 0 to release freeze I/0 */ > > dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05); > > dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04); > > -- > > 2.22.0 > >