Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Sat, 22 Jun 2019 03:18:25 -0700
From:   tip-bot for Tony W Wang-oc <tipbot@zytor.com>
Message-ID: <tip-f8c0e061cb83bd528ff0843e717bcebc846d4838@git.kernel.org>
Cc:     TonyWWang-oc@zhaoxin.com, hpa@zytor.com, tglx@linutronix.de,
        CooperYan@zhaoxin.com, gregkh@linuxfoundation.org, lenb@kernel.org,
        mingo@kernel.org, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com,
        linux-kernel@vger.kernel.org, DavidWang@zhaoxin.com,
        rjw@rjwysocki.net
Reply-To: lenb@kernel.org, gregkh@linuxfoundation.org,
          CooperYan@zhaoxin.com, rjw@rjwysocki.net, DavidWang@zhaoxin.com,
          tglx@linutronix.de, hpa@zytor.com, linux-kernel@vger.kernel.org,
          QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, mingo@kernel.org,
          TonyWWang-oc@zhaoxin.com
In-Reply-To: <a370503660994669991a7f7cda7c5e98@zhaoxin.com>
References: <a370503660994669991a7f7cda7c5e98@zhaoxin.com>
To:     linux-tip-commits@vger.kernel.org
Subject: [tip:x86/cpu] x86/acpi/cstate: Add Zhaoxin processors support for
 cache flush policy in C3
Git-Commit-ID: f8c0e061cb83bd528ff0843e717bcebc846d4838
Robot-ID: <tip-bot.git.kernel.org>
Robot-Unsubscribe: Contact <mailto:hpa@kernel.org> to get blacklisted from
 these emails
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain; charset=UTF-8
Content-Disposition: inline
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Commit-ID:  f8c0e061cb83bd528ff0843e717bcebc846d4838
Gitweb:     https://git.kernel.org/tip/f8c0e061cb83bd528ff0843e717bcebc846d4838
Author:     Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
AuthorDate: Tue, 18 Jun 2019 08:37:29 +0000
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sat, 22 Jun 2019 11:45:58 +0200

x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3

Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@zhaoxin.com

---
 arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index a5e5484988fd..caf2edccbad2 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -64,6 +64,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 		    c->x86_stepping >= 0x0e))
 			flags->bm_check = 1;
 	}
+
+	if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+		/*
+		 * All Zhaoxin CPUs that support C3 share cache.
+		 * And caches should not be flushed by software while
+		 * entering C3 type state.
+		 */
+		flags->bm_check = 1;
+		/*
+		 * On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
+		 * So, set bm_control to zero to indicate that ARB_DISABLE
+		 * is not required while entering C3 type state.
+		 */
+		flags->bm_control = 0;
+	}
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);