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[209.132.180.67]) by mx.google.com with ESMTP id 15si7909303pgm.493.2019.06.23.05.38.02; Sun, 23 Jun 2019 05:38:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726653AbfFWMhR (ORCPT + 99 others); Sun, 23 Jun 2019 08:37:17 -0400 Received: from inva021.nxp.com ([92.121.34.21]:43132 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726086AbfFWMhJ (ORCPT ); Sun, 23 Jun 2019 08:37:09 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id BE51A2003D6; Sun, 23 Jun 2019 14:37:06 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id CB38F2003CF; Sun, 23 Jun 2019 14:36:57 +0200 (CEST) Received: from mega.ap.freescale.net (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id DBC6B40313; Sun, 23 Jun 2019 20:36:46 +0800 (SGT) From: Anson.Huang@nxp.com To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, l.stach@pengutronix.de, abel.vesa@nxp.com, ccaione@baylibre.com, angus@akkea.ca, andrew.smirnov@gmail.com, agx@sigxcpu.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Linux-imx@nxp.com Subject: [PATCH RESEND V2 2/3] clocksource: imx-sysctr: Make timer work with clock driver using platform driver model Date: Sun, 23 Jun 2019 20:38:49 +0800 Message-Id: <20190623123850.22584-2-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190623123850.22584-1-Anson.Huang@nxp.com> References: <20190623123850.22584-1-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang On some i.MX8M platforms, clock driver uses platform driver model and it is NOT ready during timer initialization phase, the clock operations will fail and system counter driver will fail too. As all the i.MX8M platforms' system counter clock are from OSC which is always enabled, so it is no need to enable clock for system counter driver, the ONLY thing is to pass clock frequence to driver. To make system counter driver work for upper scenario, add an option of skipping of_clk operation for system counter driver, an optional property "clock-frequency" is introduced to pass the frequency value to system counter driver and indicate driver to skip of_clk operations. Signed-off-by: Anson Huang --- Changes since V1: - improve commit log, no content change. --- drivers/clocksource/timer-imx-sysctr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c index fd7d680..8ff3d7e 100644 --- a/drivers/clocksource/timer-imx-sysctr.c +++ b/drivers/clocksource/timer-imx-sysctr.c @@ -129,6 +129,14 @@ static void __init sysctr_clockevent_init(void) static int __init sysctr_timer_init(struct device_node *np) { int ret = 0; + u32 rate; + + if (!of_property_read_u32(np, "clock-frequency", + &rate)) { + to_sysctr.of_clk.rate = rate; + to_sysctr.of_clk.period = DIV_ROUND_UP(rate, HZ); + to_sysctr.flags &= ~TIMER_OF_CLOCK; + } ret = timer_of_init(np, &to_sysctr); if (ret) -- 2.7.4