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Date:   Mon, 24 Jun 2019 11:56:09 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Sameer Pujar <spujar@nvidia.com>
Cc:     dan.j.williams@intel.com, tiwai@suse.com, jonathanh@nvidia.com,
        dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
        sharadg@nvidia.com, rlokhande@nvidia.com, dramesh@nvidia.com,
        mkumard@nvidia.com
Subject: Re: [PATCH] [RFC] dmaengine: add fifo_size member
Message-ID: <20190624062609.GV2962@vkoul-mobl>
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On 20-06-19, 15:59, Sameer Pujar wrote:

> > > > So can you explain me what is the difference here that the peripheral
> > > > cannot configure and use burst size with passing fifo depth?
> > > Say for example FIFO_THRESHOLD is programmed as 16 WORDS, BURST_SIZE as 8
> > > WORDS.
> > > ADMAIF does not push data to AHUB(operation [2]) till threshold of 16 WORDS
> > > is
> > > reached in ADMAIF FIFO. Hence 2 burst transfers are needed to reach the
> > > threshold.
> > > As mentioned earlier, threshold here is to just indicate when data transfer
> > > can happen
> > > to AHUB modules.
> > So we have ADMA and AHUB and peripheral. You are talking to AHUB and that
> > is _not_ peripheral and if I have guess right the fifo depth is for AHUB
> > right?
> Yes the communication is between ADMA and AHUB. ADMAIF is the interface
> between
> ADMA and AHUB. ADMA channel sending data to AHUB pairs with ADMAIF TX
> channel.
> Similary ADMA channel receiving data from AHUB pairs with ADMAIF RX channel.
> FIFO DEPTH we are talking is about each ADMAIF TX/RX channel and it is
> configurable.
> DMA transfers happen to/from ADMAIF FIFOs and whenever data(per WORD) is
> popped/pushed
> out of ADMAIF to/from AHUB, asseration is made to ADMA. ADMA keeps counters
> based on
> these assertions. By knowing FIFO DEPTH and these counters, ADMA knows when
> to wait or
> when to transfer data.

Where does ADMAIF driver reside in kernel, who configures it for normal
dma txns..?

Also it wold have helped the long discussion if that part was made clear
rather than talking about peripheral all this time :(

-- 
~Vinod