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[209.132.180.67]) by mx.google.com with ESMTP id b7si12969649pgt.117.2019.06.24.21.06.55; Mon, 24 Jun 2019 21:07:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=UXhIQBFY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729234AbfFYAcz (ORCPT + 99 others); Mon, 24 Jun 2019 20:32:55 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:46743 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727295AbfFYAcz (ORCPT ); Mon, 24 Jun 2019 20:32:55 -0400 Received: by mail-ed1-f68.google.com with SMTP id d4so24257883edr.13 for ; Mon, 24 Jun 2019 17:32:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nBkBYYZc0s8xxqgkIM92IszAEEryF8hhcj8JV1SU20A=; b=UXhIQBFYD2yMmcFMLp1puhsD2i9OksoE0tmnxr7K5BnwgNkxdyzcQboUIz9i20Lsz4 3m1RTIe30lWE24I7cvsZZLLhkZgDOCOIkk9ZbG6EosmpUQjxEvoya52YQrtLyV7zH9ed epQ9slu7TgFvXvJ/O6QSeC0l0d5tfQ1BjsfsF+SeCivQZbElS/gZ18iF66YuOrQ/JcOD zhFe4na0F79DpVOMYVK7Dpm3S34HraMbgjpZtfCF2h2d+s5CnnYrRGOohH7RQ9Wj0HSM Xurwf4MZJZS7xJOqWZLSW/LSVgkO36dAgq2GlDTSVHZBaAcm83Tu0TMT9EcFBYadyl+r OB+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nBkBYYZc0s8xxqgkIM92IszAEEryF8hhcj8JV1SU20A=; b=GL8zZtSaBo8SMsAfjBblh400o+9X+DsXC9gtYPk8nKh8S3kIAgnsw2VCL3V1tX+srK sZcosO96E+3an8wzvIQWDBXJ+PhYYBvuMnEvUTtcKZ9fdHICtjPQ7MlVGerlql2s21fG oNHRoz+skuimbbEu7jFSpEPquhX5FV+lDADgT7rEJcvp0nCz71UIfBBEH88slw5DLSDt QpHntHLUIOv0l0b7lciSzWL62n+O7o126OHTT6/Xy4CVbM0ayWyLkPUs6Rp9gSKU56Cm kBubcvHVi7W0WPuCbN2DZ+avXDWZTOE6T2Gw+wmjxaCZ/99q2l0aejD6/xFWyApuHedF EJ7A== X-Gm-Message-State: APjAAAU8cWAphHkg/Xy0hzI8oKpIgPYkAI9ZD/1h2CFuFcfJ3zfEomRR cu/o6Ba3rvTFKyMUN+RjZvgwCWqYg1Oda3D5rUsqRA== X-Received: by 2002:aa7:cdc6:: with SMTP id h6mr80176428edw.5.1561422773047; Mon, 24 Jun 2019 17:32:53 -0700 (PDT) MIME-Version: 1.0 References: <5D036843.2010607@intel.com> In-Reply-To: <5D036843.2010607@intel.com> From: Eric Hankland Date: Mon, 24 Jun 2019 17:32:41 -0700 Message-ID: Subject: Re: [PATCH v1] KVM: x86: PMU Whitelist To: Wei Wang Cc: Paolo Bonzini , rkrcmar@redhat.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks for your feedback - I'll send out an updated version incorporating your comments shortly (assuming you don't have more after this). > > +struct kvm_pmu_whitelist { > > + __u64 event_mask; > > Is this "ARCH_PERFMON_EVENTSEL_EVENT | ARCH_PERFMON_EVENTSEL_UMASK"? In most cases, I envision this being the case, but it's possible users may want other bits - see response to the next question below. > > + __u16 num_events; > > + __u64 events[0]; > > Can this be __u16? > The lower 16 bits (umask+eventsel) already determines what the event is. It looks like newer AMD processors also use bits 32-35 for eventsel (see AMD64_EVENTSEL_EVENT/AMD64_RAW_EVENT_MASK in arch/x86/include/asm/perf_event.h or a recent reference guide), though it doesn't look like this has made it to pmu_amd.c in kvm yet. Further, including the whole 64 bits could enable whitelisting some events with particular modifiers (e.g. in_tx=0, but not in_tx=1). I'm not sure if whitelisting with specific modifiers will be necessary, but we definitely need more than u16 if we want to support any AMD events that make use of those bits in the future. > > + struct kvm_pmu_whitelist *whitelist; > > This could be per-VM and under rcu? I'll try this out in the next version. > Why not moving this filter to reprogram_gp_counter? > > You could directly compare "unit_mask, event_sel" with whitelist->events[i] The reason is that this approach provides uniform behavior whether an event is programmed on a fixed purpose counter vs a general purpose one. Though I admit it's unlikely that instructions retired/cycles wouldn't be whitelisted (and ref cycles can't be programmed on gp counters), so it wouldn't be missing too much if I do move this to reprogram_gp_counter. What do you think? > I would directly return -EFAULT here. > > Same here. Sounds good - I'll fix that in the next version. > > + pmu->whitelist = new; > > Forgot to copy the whitelist-ed events to new? Yep, somehow I deleted the lines that did this - thanks for pointing it out.