Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Wed, 26 Jun 2019 09:55:31 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     "Phillips, Kim" <kim.phillips@amd.com>
Cc:     Ingo Molnar <mingo@redhat.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "stable@vger.kernel.org" <stable@vger.kernel.org>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@redhat.com>,
        Namhyung Kim <namhyung@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>,
        "H. Peter Anvin" <hpa@zytor.com>, Martin Liska <mliska@suse.cz>,
        "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>,
        "Natarajan, Janakarajan" <Janakarajan.Natarajan@amd.com>,
        "Hook, Gary" <Gary.Hook@amd.com>, Pu Wen <puwen@hygon.cn>,
        Stephane Eranian <eranian@google.com>,
        Vince Weaver <vincent.weaver@maine.edu>,
        "x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 1/2 RESEND2] perf/x86/amd/uncore: Do not set ThreadMask
 and SliceMask for non-L3 PMCs
Message-ID: <20190626075531.GG3419@hirez.programming.kicks-ass.net>
References: <20190625145548.11600-1-kim.phillips@amd.com>
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On Tue, Jun 25, 2019 at 02:56:23PM +0000, Phillips, Kim wrote:
> From: Kim Phillips <kim.phillips@amd.com>
> 
> Commit d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask
> for L3 Cache perf events") enables L3 PMC events for all threads and
> slices by writing 1s in ChL3PmcCfg (L3 PMC PERF_CTL) register fields.
> 
> Those bitfields overlap with high order event select bits in the Data
> Fabric PMC control register, however.
> 
> So when a user requests raw Data Fabric events (-e amd_df/event=0xYYY/),
> the two highest order bits get inadvertently set, changing the counter
> select to events that don't exist, and for which no counts are read.
> 
> This patch changes the logic to write the L3 masks only when dealing
> with L3 PMC counters.
> 
> AMD Family 16h and below Northbridge (NB) counters were not affected.
> 
> Signed-off-by: Kim Phillips <kim.phillips@amd.com>

Still base64 encoded garbage; the actual email reads like below.

Please use a sane MUa and send it plain text.

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