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[77.130.92.26]) by smtp.googlemail.com with ESMTPSA id w7sm1110780wmc.46.2019.06.26.03.37.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 03:37:54 -0700 (PDT) Subject: Re: [PATCH RESEND V2 1/3] clocksource/drivers/sysctr: Add optional clock-frequency property To: Anson Huang , "tglx@linutronix.de" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "l.stach@pengutronix.de" , Abel Vesa , "ccaione@baylibre.com" , "angus@akkea.ca" , "andrew.smirnov@gmail.com" , "agx@sigxcpu.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Cc: dl-linux-imx References: <20190623123850.22584-1-Anson.Huang@nxp.com> <55abafbd-c010-32b5-6d76-26040830d5b0@linaro.org> From: Daniel Lezcano Openpgp: preference=signencrypt Autocrypt: addr=daniel.lezcano@linaro.org; prefer-encrypt=mutual; keydata= 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a+0AjSGd886Bh0kT1Dznrite0dzYlTHlacbITZG84yRk/gS7DkYQdjL8zgFr/pxH5CbYJDk0 tYUhisTESeesbvWSPO5uNqqy1dAFw+dqRcF5gXIh3NKX0gqiAA87NM7nL5ym/CNpJ7z7nRC8 qePOXubgouxumi5RQs1+crBmCDa/AyJHKdG2mqCt9fx5EPbDpw6Zzx7hgURh4ikHoS7/tLjK iqWjuat8/HWc01yEd8rtkGuUcMqbCi1XhcAmkaOnX8FYscMRoyyMrWClRZEQRokqZIj79+PR adkDXtr4MeL8BaB7Ij2oyRVjXUwhFQNKi5Z5Rve0a3zvGkkqw8Mz20BOksjSWjAF6g9byukl CUVjC03PdMSufNLK06x5hPc/c4tFR4J9cLrV+XxdCX7r0zGos9SzTPGNuIk1LK++S3EJhLFj 4eoWtNhMWc1uiTf9ENza0ntqH9XBWEQ6IA1gubCniGG+Xg== Message-ID: <9c017ba9-ac6b-480b-d1f3-120289343101@linaro.org> Date: Wed, 26 Jun 2019 12:37:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26/06/2019 03:42, Anson Huang wrote: > Hi, Daniel > >> On 23/06/2019 14:38, Anson.Huang@nxp.com wrote: >>> From: Anson Huang >>> >>> Systems which use platform driver model for clock driver require the >>> clock frequency to be supplied via device tree when system counter >>> driver is enabled. >>> >>> This is necessary as in the platform driver model the of_clk >>> operations do not work correctly because system counter driver is >>> initialized in early phase of system boot up, and clock driver using >>> platform driver model is NOT ready at that time, it will cause system >>> counter driver initialization failed. >>> >>> Add the optinal clock-frequency to the device tree bindings of the NXP >>> system counter, so the frequency can be handed in and the of_clk >>> operations can be skipped. >> >> Isn't it possible to create a fixed-clock and refer to it? So no need to create a >> specific action before calling timer_of_init() ? >> > > As the clock must be ready before the TIMER_OF_DECLARE, so adding a CLK_OF_DECLARE_DRIVER in > clock driver to ONLY register a fixed-clock? The system counter's frequency are different on different > platforms, so adding fixed clock in system counter driver is NOT a good idea, ONLY the DT node or the > clock driver can create this fixed clock according to platforms, can you advise where to create this fixed > clock is better? Can you point me to a DT with the "nxp,sysctr-timer" ? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog