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received-spf: None (protection.outlook.com: xilinx.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: xKrwr4yQu5c9md0EZnBaWhCqMdnkVfKN1XkOMeE/JjUVXoCHdXbHp6gzZ/9U4gDaKXUjjzXQ4yTKTNEAFRqyTK6uimS2YHxSX4VroGWN6QdBPDEg+m69nIpDnYAoFO5QFdGa7Er4nG/XBKVrjlHIYhS6zCuMJuCUeRNmpun6zqN8ti1JwAH28qFSYBYuthEERl07AISpLlovVGjd+diCgLEPNk7Y0FBRDymD+ISVy0J+3aiQIOE3qDvgM3HhRAv3CEuAQoLNUGJo6hd7GSgOdTE12Ghk/IiERMTkLHDpVYHRfsa4ef7hDw3rvJh/EjaRIBwuGP3Zx7KKycuBXYBkkntEVOrGp3pvZ5jEdTXS5ZS3wlOnfIb+kzMDWLtF93VTmLCekM5r14hCAucJc3E3xZjURLRkTN1jtysAGragDxE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: e3c7b4b6-b0fc-498e-a169-08d6fa2f9a55 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Jun 2019 12:12:47.7794 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nagasure@xilinx.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4540 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Boris, > -----Original Message----- > From: Boris Brezillon > Sent: Wednesday, June 26, 2019 5:34 PM > To: Naga Sureshkumar Relli > Cc: miquel.raynal@bootlin.com; helmut.grohne@intenta.de; richard@nod.at; > dwmw2@infradead.org; computersforpeace@gmail.com; marek.vasut@gmail.com; > vigneshr@ti.com; bbrezillon@kernel.org; yamada.masahiro@socionext.com; li= nux- > mtd@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [LINUX PATCH v17 1/2] mtd: rawnand: nand_micron: Do not over= write > driver's read_page()/write_page() >=20 > On Wed, 26 Jun 2019 11:51:12 +0000 > Naga Sureshkumar Relli wrote: >=20 > > Hi Boris, > > > > > -----Original Message----- > > > From: Boris Brezillon > > > Sent: Wednesday, June 26, 2019 4:57 PM > > > To: Naga Sureshkumar Relli > > > Cc: miquel.raynal@bootlin.com; helmut.grohne@intenta.de; > > > richard@nod.at; dwmw2@infradead.org; computersforpeace@gmail.com; > > > marek.vasut@gmail.com; vigneshr@ti.com; bbrezillon@kernel.org; > > > yamada.masahiro@socionext.com; linux- mtd@lists.infradead.org; > > > linux-kernel@vger.kernel.org > > > Subject: Re: [LINUX PATCH v17 1/2] mtd: rawnand: nand_micron: Do not > > > over write driver's read_page()/write_page() > > > > > > On Wed, 26 Jun 2019 11:22:33 +0000 > > > Naga Sureshkumar Relli wrote: > > > > > > > Hi Boris, > > > > > > > > > -----Original Message----- > > > > > From: Boris Brezillon > > > > > Sent: Wednesday, June 26, 2019 12:18 PM > > > > > To: Naga Sureshkumar Relli > > > > > Cc: miquel.raynal@bootlin.com; helmut.grohne@intenta.de; > > > > > richard@nod.at; dwmw2@infradead.org; > > > > > computersforpeace@gmail.com; marek.vasut@gmail.com; > > > > > vigneshr@ti.com; bbrezillon@kernel.org; > > > > > yamada.masahiro@socionext.com; linux- mtd@lists.infradead.org; > > > > > linux-kernel@vger.kernel.org > > > > > Subject: Re: [LINUX PATCH v17 1/2] mtd: rawnand: nand_micron: Do > > > > > not over write driver's read_page()/write_page() > > > > > > > > > > On Mon, 24 Jun 2019 22:46:29 -0600 Naga Sureshkumar Relli > > > > > wrote: > > > > > > > > > > > Add check before assigning chip->ecc.read_page() and > > > > > > chip->ecc.write_page() > > > > > > > > > > > > Signed-off-by: Naga Sureshkumar Relli > > > > > > > > > > > > --- > > > > > > drivers/mtd/nand/raw/nand_micron.c | 7 +++++-- > > > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git a/drivers/mtd/nand/raw/nand_micron.c > > > > > > b/drivers/mtd/nand/raw/nand_micron.c > > > > > > index cbd4f09ac178..565f2696c747 100644 > > > > > > --- a/drivers/mtd/nand/raw/nand_micron.c > > > > > > +++ b/drivers/mtd/nand/raw/nand_micron.c > > > > > > @@ -500,8 +500,11 @@ static int micron_nand_init(struct nand_ch= ip *chip) > > > > > > chip->ecc.size =3D 512; > > > > > > chip->ecc.strength =3D chip->base.eccreq.strength; > > > > > > chip->ecc.algo =3D NAND_ECC_BCH; > > > > > > - chip->ecc.read_page =3D micron_nand_read_page_on_die_ecc; > > > > > > - chip->ecc.write_page =3D micron_nand_write_page_on_die_ecc; > > > > > > + if (!chip->ecc.read_page) > > > > > > + chip->ecc.read_page =3D micron_nand_read_page_on_die_ecc; > > > > > > + > > > > > > + if (!chip->ecc.write_page) > > > > > > + chip->ecc.write_page =3D micron_nand_write_page_on_die_ecc; > > > > > > > > > > That's wrong, if you don't want on-die ECC to be used, simply > > > > > don't set nand-ecc-mode to "on- die". > > > > Ok. But if we want to use on-die ECC then you mean to say it is > > > > mandatory to use > > > micron_nand_read/write_page_on_die_ecc()? > > > > > > Absolutely, and if it doesn't work that means you driver does not > > > implement raw accesses correctly, which means it's still buggy... > > I agree. But let's say, if there is a limitation with the controller. T= hen it is must to have this > check right? > > I mean, for pl353 controller, we must clear the CS during the data > > phase, hence we are splitting the Transfer in the pl353_read/write_page= _raw(). > > + pl353_nand_read_data_op(chip, buf, mtd->writesize, false); > > + p =3D chip->oob_poi; > > + pl353_nand_read_data_op(chip, p, > > + (mtd->oobsize - > > + PL353_NAND_LAST_TRANSFER_LENGTH), false); > > + p +=3D (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH); > > + xnfc->dataphase_addrflags |=3D PL353_NAND_CLEAR_CS; > > + pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH, > > + false); > > As the above sequence is needed even for raw access, PL353 is unable to= use the on_die_page > reads. >=20 > This "de-assert CS on last access" logic should be done in the > exec_op() implementation. I also wonder how that works for operations tha= t don't have data > cycles. Oh, BTW, most chips are CE-don't-care, which means you can assert= /de-assert CS on > each read_data_op() without any issues. Yes, we can assert/de-assert CS on each read/write_data_op(). But what about transfer length splitting? + p =3D chip->oob_poi; + pl353_nand_read_data_op(chip, p, + (mtd->oobsize - + PL353_NAND_LAST_TRANSFER_LENGTH), false); + p +=3D (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH); This should be done as a part of pl353_raw_read/write() right? Thanks, Naga Sureshkumar Relli