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[73.95.159.87]) by smtp.gmail.com with ESMTPSA id d17sm206248iom.28.2019.06.26.14.01.24 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 26 Jun 2019 14:01:25 -0700 (PDT) Date: Wed, 26 Jun 2019 14:01:23 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Rob Herring cc: linux-riscv@lists.infradead.org, "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] dt-bindings: riscv: resolve 'make dt_binding_check' warnings In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 26 Jun 2019, Paul Walmsley wrote: > On Wed, 26 Jun 2019, Rob Herring wrote: > > > On Wed, Jun 26, 2019 at 9:30 AM Paul Walmsley wrote: > > > > > > Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema > > > results in warnings from 'make dt_binding_check'. Fix these. > > > > > > While here, make the whitespace in the second example consistent with the > > > first example. > > > > > > Signed-off-by: Paul Walmsley > > > Cc: Rob Herring > > > --- > > > .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- > > > 1 file changed, 14 insertions(+), 12 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index 27f02ec4bb45..f97a4ecd7b91 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -152,17 +152,19 @@ examples: > > > - | > > > // Example 2: Spike ISA Simulator with 1 Hart > > > cpus { > > > - cpu@0 { > > > - device_type = "cpu"; > > > - reg = <0>; > > > - compatible = "riscv"; > > > - riscv,isa = "rv64imafdc"; > > > - mmu-type = "riscv,sv48"; > > > - interrupt-controller { > > > - #interrupt-cells = <1>; > > > - interrupt-controller; > > > - compatible = "riscv,cpu-intc"; > > > - }; > > > - }; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + cpu@0 { > > > > This only works because you removed 'cpus' and therefore none of this > > schema is applied. > > I'm not following you - could you point out where "cpus" was removed? If it helps, this patch is simply to fix the dtc warnings that you mentioned in your post on devicetree-spec@. Without this patch, with "make dtbs_check", the following warnings are generated: DTC Documentation/devicetree/bindings/riscv/cpus.example.dtb Documentation/devicetree/bindings/riscv/cpus.example.dts:75.25-35: Warning (reg_format): /example-1/cpus/cpu@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Documentation/devicetree/bindings/riscv/cpus.example.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' Documentation/devicetree/bindings/riscv/cpus.example.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' Documentation/devicetree/bindings/riscv/cpus.example.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' Documentation/devicetree/bindings/riscv/cpus.example.dts:73.23-84.19: Warning (avoid_default_addr_size): /example-1/cpus/cpu@0: Relying on default #address-cells value Documentation/devicetree/bindings/riscv/cpus.example.dts:73.23-84.19: Warning (avoid_default_addr_size): /example-1/cpus/cpu@0: Relying on default #size-cells value When the patch is applied, dtc doesn't report any of these warnings. Let me know if I'm missing something obvious. - Paul