Received: by 2002:a25:f815:0:0:0:0:0 with SMTP id u21csp1625476ybd; Wed, 26 Jun 2019 22:02:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqx1VpfsDZ+vJ0fEBkj7BAiq5PdPZDhQdjYwZWh2g/pVdPp9Au8ESzQhRi8ENm79f9/FRgPH X-Received: by 2002:a17:902:848b:: with SMTP id c11mr2245944plo.217.1561611747731; Wed, 26 Jun 2019 22:02:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561611747; cv=none; d=google.com; s=arc-20160816; b=lxhEiR0sMl20riOwXxcKLTgSp+2POU399WDNhrnYWNjbMsbQdVGaEnJvcIzFHyxI/6 65/ZvxnpRudSVp2Y3VRKhc0d7N8ItDAvWiVmSi5f8w/Ux3m5VezcluLTJFm6dYpD1gOF qOn1Mq4aXgnJNSBHKjj0pMxMN/mfiPa5zJKvlrYYN9yD8UpUZHyzByPxwy9SNemmWURw KcGQxNcXya2hCQqoVRdw0wtowX235Qt8JEVQD4yfFk+sECTwxsd4jJFW25TRPbM1Rcvv C5TWmZLrBlFKrrYdv6Uc+zr9iTSUQJWTLJUJARLAt2j9TM1LZy+2C36Cxwo4foaPV8kF LjtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=UUIOfviT+bn6NFrQfK3BpZAy0Skz6MWwpbccyj84Mgo=; b=PXKLad/Koyjg+IYcGQs3iRrvejqXNulEqKFv1+e/QCUQHTTH9tTy/BRtQFrnEor6Gx Z4vclI+/48S9JBBco+sSdEm63vrzsvzvyiM3sAoYIq0MvSF/G8sXGrWgNL8mvZ1b3Suf zm+7j7wBC+tLbNX2rs/WGZz/JewqbFs0ZEaTnOIidU2kp3CNnJzxfksV+uMisKIA5Hd8 MsQheL7WZIBogTS63tRLc9+bjxLhErDB8wPS4tpNAYBxV2sJbTkzPss5/9scl4+1ML+G TK26UrkaOMHPnYGzSvDYHiQSRv9uGCzNwbWKqzSRUrkvOjD0dFrDisWorMAKRvEpPuPR 77SQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e25si1677177pff.30.2019.06.26.22.01.59; Wed, 26 Jun 2019 22:02:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727208AbfF0FBw (ORCPT + 99 others); Thu, 27 Jun 2019 01:01:52 -0400 Received: from mga11.intel.com ([192.55.52.93]:22916 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726563AbfF0FBw (ORCPT ); Thu, 27 Jun 2019 01:01:52 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2019 22:01:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,422,1557212400"; d="scan'208";a="173005017" Received: from hao-dev.bj.intel.com ([10.238.157.65]) by orsmga002.jf.intel.com with ESMTP; 26 Jun 2019 22:01:49 -0700 From: Wu Hao To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-api@vger.kernel.org, yilun.xu@intel.com, hao.wu@intel.com, gregkh@linuxfoundation.org, atull@kernel.org Subject: [PATCH v4 01/15] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address. Date: Thu, 27 Jun 2019 12:44:41 +0800 Message-Id: <1561610695-5414-2-git-send-email-hao.wu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561610695-5414-1-git-send-email-hao.wu@intel.com> References: <1561610695-5414-1-git-send-email-hao.wu@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org FME_PR_INTFC_ID is used as compat_id for fpga manager and region, but high 64 bits and low 64 bits of the compat_id are swapped by mistake. This patch fixes this problem by fixing register address. Signed-off-by: Wu Hao Acked-by: Alan Tull Acked-by: Moritz Fischer --- drivers/fpga/dfl-fme-mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c index 76f3770..b3f7eee 100644 --- a/drivers/fpga/dfl-fme-mgr.c +++ b/drivers/fpga/dfl-fme-mgr.c @@ -30,8 +30,8 @@ #define FME_PR_STS 0x10 #define FME_PR_DATA 0x18 #define FME_PR_ERR 0x20 -#define FME_PR_INTFC_ID_H 0xA8 -#define FME_PR_INTFC_ID_L 0xB0 +#define FME_PR_INTFC_ID_L 0xA8 +#define FME_PR_INTFC_ID_H 0xB0 /* FME PR Control Register Bitfield */ #define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */ -- 1.8.3.1