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[209.132.180.67]) by mx.google.com with ESMTP id u67si1420610pgu.219.2019.06.27.00.07.23; Thu, 27 Jun 2019 00:07:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726563AbfF0HFc (ORCPT + 99 others); Thu, 27 Jun 2019 03:05:32 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:33285 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726049AbfF0HFb (ORCPT ); Thu, 27 Jun 2019 03:05:31 -0400 Received: from lupine.hi.pengutronix.de ([2001:67c:670:100:3ad5:47ff:feaf:1a17] helo=lupine) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1hgOTI-0007Bx-DH; Thu, 27 Jun 2019 09:05:28 +0200 Message-ID: <1561619128.4216.3.camel@pengutronix.de> Subject: Re: [PATCH] reset: Add driver for dispmix reset From: Philipp Zabel To: Fancy Fang , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" Cc: "festevam@gmail.com" , "kernel@pengutronix.de" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , dl-linux-imx Date: Thu, 27 Jun 2019 09:05:28 +0200 In-Reply-To: References: <20190625055557.7507-1-chen.fang@nxp.com> <1561474623.5559.4.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1+deb9u2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2019-06-26 at 06:46 +0000, Fancy Fang wrote: [...] > > The same goes for the clock soft enable bits on i.MX8MM. If those > > bits actually control clock gates, they should not be described as > > reset controls in the device tree. > > [FF] Make sense. The functions provided by the "dispmix reset" is more > likely to be a combination of a clock gating module and a reset > control than a standard reset controller. The reason why I choose > reset framework to implement this device is that: First, this module > is named as "dispmix reset" in the dispmix's design spec, so it gives > me the first impression that it should be acted as a reset controller. > And I'll check this with the IC designer. Thank you. > Second, the "dispmix reset" is separated from the CCM LPCG module > which is used as the only clock controller device for the whole > platform. So the CCM clock driver seems cannot cover this device. > Last, the "dispmix reset" is shared by all the submodules in the > dispmix, so I abstract this device to be a reset controller driver to > simplify the 'reset' logic for all the submodules drivers. Agreed on both points. > If using clock framework to cover this device, another driver needs to > be implemented. I'll take a close look at it to see if this can > happen. Yes, if my assumptions are correct, it would be good if this could be rewritten as a combined clock and reset driver. There are quite a few examples for this in drivers/clk already. [...] > > Is there any reason not to just use straight readl/writel besides > > the automatic clock handling? > > [FF] Use regmap is for simplifying the register modifications since > the register has no SET or CLR shadow, so when set or clear one bit, > the register needs to be read-and-modify. And besides, the register > access requires disp-apb clock open, and regmap can handle this > properly. Ok, this makes sense to me. regards Philipp