Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Thu, 27 Jun 2019 18:59:01 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Christophe Kerello <christophe.kerello@st.com>
Cc:     <richard@nod.at>, <dwmw2@infradead.org>,
        <computersforpeace@gmail.com>, <marek.vasut@gmail.com>,
        <vigneshr@ti.com>, <bbrezillon@kernel.org>,
        <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <linux-stm32@st-md-mailman.stormreply.com>,
        Amelie Delaunay <amelie.delaunay@st.com>
Subject: Re: [PATCH] mtd: rawnand: stm32_fmc2: increase DMA completion
 timeouts
Message-ID: <20190627185901.6247a77c@xps13>
In-Reply-To: <1561128480-14531-1-git-send-email-christophe.kerello@st.com>
References: <1561128480-14531-1-git-send-email-christophe.kerello@st.com>
Organization: Bootlin
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8BIT
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Hi Christophe,

Christophe Kerello <christophe.kerello@st.com> wrote on Fri, 21 Jun
2019 16:48:00 +0200:

> When the system is overloaded, DMA data transfer completion occurs after
> 100ms. Increase the timeouts to let it the time to complete.
> 
> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>

The first SoB should be the author's. Either Amelie is the author and
you should use 'git commit --amend --author=..." or she is not and
should be dropped (unless she sends the patch which is yours, and in
this case her name should appear second).

> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
> ---
>  drivers/mtd/nand/raw/stm32_fmc2_nand.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> index 4aabea2..c7f7c6f 100644
> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> @@ -981,7 +981,7 @@ static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf,
>  
>  	/* Wait DMA data transfer completion */
>  	if (!wait_for_completion_timeout(&fmc2->dma_data_complete,
> -					 msecs_to_jiffies(100))) {
> +					 msecs_to_jiffies(500))) {
>  		dev_err(fmc2->dev, "data DMA timeout\n");
>  		dmaengine_terminate_all(dma_ch);
>  		ret = -ETIMEDOUT;
> @@ -990,7 +990,7 @@ static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf,
>  	/* Wait DMA ECC transfer completion */
>  	if (!write_data && !raw) {
>  		if (!wait_for_completion_timeout(&fmc2->dma_ecc_complete,
> -						 msecs_to_jiffies(100))) {
> +						 msecs_to_jiffies(500))) {

IIRC I already asked you this but could you please make a define and at
the same time make it 1000 ms, I don't see the point in being close
to the maximum latency. If this is reached, your transfer was
screwed already, there is no performance impact here.

Sorry for the late notice but I will close the nand/next branch
tomorrow, so I'll queue your v2 only if I receive it soon enough :)

Thanks,
Miquèl