Received: by 2002:a25:f815:0:0:0:0:0 with SMTP id u21csp2760046ybd;
        Thu, 27 Jun 2019 19:15:11 -0700 (PDT)
X-Google-Smtp-Source: APXvYqwB9V4hR60MTMsoOttphLwaBylm8D5KvbrvCLjLl9i/po28MU922k+hpEbc702BItNFcauS
X-Received: by 2002:a17:902:8509:: with SMTP id bj9mr8518236plb.79.1561688111675;
        Thu, 27 Jun 2019 19:15:11 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1561688111; cv=none;
        d=google.com; s=arc-20160816;
        b=h+cWFhtBREO4krbLKKUbyTSHea62ZEOYooTLgukdJz2Jjb/Fs4yRYEmRkiJIGywkQm
         uwYSr9YjAbRV0XpYZB+XGIX00PwnOtGQuxLziZppfGGMCqDcPmqlMJsnhsrV4KVt1q1s
         zjIRBk+1tnESbcdmeUc/14BzboTsZ0oE22OadJVB5ZX8Lvs2+xT5F+LEfsaokXxc39GA
         IBwQJkEXVvEcpC4j6NgR8sMkPy5YgJHPol9mJM1m9C9jkIyNBNw7BYqywaMaCvZQvVJ1
         qVWRbqaaRzvzau791sYeNgW8TB4Ckq+LmSAbe5Igrc/nzrlxLiQZTj8ghcxAGZe32LfW
         a0eg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=yMF0oM3+uebVoba25pi7TTeIEke1092zLym6YFQg1MQ=;
        b=EMXQzoFlOcKm5OZB0nzngEmOW47l+A23QBRXZXemzsUgYTgYj1imzV4CHqJ0XcxkWk
         W5VqstYWZWCdFNl2sWlXtFz8WczxxzPEVYvBqEi0XGW2rNrKnMYvJOlJc8A/TEDJp4kr
         uGN9sUM+4/jz8OuDhXCcET6XxTRb+baIQhrkoLAfZtxH8bFRE7RQbyztlzGSQ9L2qnS1
         wHilhzcRTZ7M0iycgOA55M5k66gTTzSDv92H0CnbD60uOl22lrHf0Dz0JculvkCjZO2t
         Yg51jLmuaYE5r3/kypav5kMJ2plAVbj5amJXSJj+ntpP9yQLu9jMN+v5f/u6iXLOsmYY
         f7BQ==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=rbiOVfdp;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id f12si780498plr.211.2019.06.27.19.14.56;
        Thu, 27 Jun 2019 19:15:11 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=rbiOVfdp;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1726828AbfF1CN6 (ORCPT <rfc822;zeqiangyin@gmail.com>
        + 99 others); Thu, 27 Jun 2019 22:13:58 -0400
Received: from hqemgate15.nvidia.com ([216.228.121.64]:5511 "EHLO
        hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1726659AbfF1CNi (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Thu, 27 Jun 2019 22:13:38 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5d1577d30000>; Thu, 27 Jun 2019 19:13:39 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Thu, 27 Jun 2019 19:13:36 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:36 -0700
Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun
 2019 02:13:36 +0000
Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Fri, 28 Jun 2019 02:13:36 +0000
Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5d1577d00000>; Thu, 27 Jun 2019 19:13:36 -0700
From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
        <tglx@linutronix.de>, <jason@lakedaemon.net>,
        <marc.zyngier@arm.com>, <linus.walleij@linaro.org>,
        <stefan@agner.ch>, <mark.rutland@arm.com>
CC:     <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
        <sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
        <linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
        <josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,
        <digetx@gmail.com>, <devicetree@vger.kernel.org>
Subject: [PATCH V5 16/18] soc/tegra: pmc: Configure deep sleep control settings
Date:   Thu, 27 Jun 2019 19:12:50 -0700
Message-ID: <1561687972-19319-17-git-send-email-skomatineni@nvidia.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com>
References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1561688019; bh=yMF0oM3+uebVoba25pi7TTeIEke1092zLym6YFQg1MQ=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=rbiOVfdp9R58xH6NOj1wyxEfUXrvoVQ4oE+jg12coxJfKKYW7y4QI1YtDtA26wD4j
         qQaaK/Cwx+YNLTCrd4NqzNXNPi0sk5mw63k9GVlBfbLBkvi4TIhW9h2ISuraD+UUxV
         bj5ZuRoHsqaW1SBSru1aR1k+TGuzeCdRDF14JbhKiinI8XgbUCvhX7RC3kFzE16u5l
         qPPxqB9B/dHcQyyG1Uj16Nibe77Ub54bOGAMo/IM4SkXH6NhQ+sbPu94b/JWpeaz6Y
         Sy+M6V8aIH4u1MZw20+fHSdq+VQG6fO6Z6xnoL395IP4oHNzIe1MDbO8/SEk2IZgWQ
         qsSpkg16ceA1A==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
timings which are platform specific that should be configured before
entering into deep sleep.

Below are the timing specific configurations for deep sleep entry and
wakeup.
- Core rail power-on stabilization timer
- OSC clock stabilization timer after SOC rail power is stabilized.
- Core power off time is the minimum wake delay to keep the system
  in deep sleep state irrespective of any quick wake event.

These values depends on the discharge time of regulators and turn OFF
time of the PMIC to allow the complete system to finish entering into
deep sleep state.

These values vary based on the platform design and are specified
through the device tree.

This patch has implementation to configure these timings which are must
to have for proper deep sleep and wakeup operations.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/soc/tegra/pmc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index ed83c0cd09a3..7e4a8f04f4c4 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -89,6 +89,8 @@
 
 #define PMC_CPUPWRGOOD_TIMER		0xc8
 #define PMC_CPUPWROFF_TIMER		0xcc
+#define PMC_COREPWRGOOD_TIMER		0x3c
+#define PMC_COREPWROFF_TIMER		0xe0
 
 #define PMC_PWR_DET_VALUE		0xe4
 
@@ -2291,6 +2293,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = {
 static void tegra20_pmc_init(struct tegra_pmc *pmc)
 {
 	u32 value;
+	unsigned long osc, pmu, off;
 
 	/* Always enable CPU power request */
 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
@@ -2316,6 +2319,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
 	value |= PMC_CNTRL_SYSCLK_OE;
 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
+
+	osc = DIV_ROUND_UP_ULL(pmc->core_osc_time * 8192, 1000000);
+	pmu = DIV_ROUND_UP_ULL(pmc->core_pmu_time * 32768, 1000000);
+	off = DIV_ROUND_UP_ULL(pmc->core_off_time * 32768, 1000000);
+	if (osc && pmu)
+		tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
+				 PMC_COREPWRGOOD_TIMER);
+	if (off)
+		tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
 }
 
 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
-- 
2.7.4