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[109.80.100.86]) by smtp.gmail.com with ESMTPSA id c1sm10896319wrh.1.2019.06.29.08.12.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Jun 2019 08:12:43 -0700 (PDT) Date: Sat, 29 Jun 2019 17:12:36 +0200 From: Andrea Parri To: Steven Rostedt Cc: Byungchul Park , "Paul E. McKenney" , Scott Wood , Joel Fernandes , Sebastian Andrzej Siewior , rcu , LKML , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Josh Triplett , Mathieu Desnoyers , Lai Jiangshan Subject: Re: [RFC] Deadlock via recursive wakeup via RCU with threadirqs Message-ID: <20190629151236.GA7862@andrea> References: <20190627155506.GU26519@linux.ibm.com> <20190627173831.GW26519@linux.ibm.com> <20190627181638.GA209455@google.com> <20190627184107.GA26519@linux.ibm.com> <13761fee4b71cc004ad0d6709875ce917ff28fce.camel@redhat.com> <20190627203612.GD26519@linux.ibm.com> <20190628073138.GB13650@X58A-UD3R> <20190628104045.GA8394@X58A-UD3R> <20190628114411.5d9ab351@gandalf.local.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190628114411.5d9ab351@gandalf.local.home> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Steve, > As Paul stated, interrupts are synchronization points. Archs can only > play games with ordering when dealing with entities outside the CPU > (devices and other CPUs). But if you have assembly that has two stores, > and an interrupt comes in, the arch must guarantee that the stores are > done in that order as the interrupt sees it. Hopefully I'm not derailing the conversation too much with my questions ... but I was wondering if we had any documentation (or inline comments) elaborating on this "interrupts are synchronization points"? Thanks, Andrea