Date: Tue, 29 Nov 2005 10:09:03 -0800
From: Stephane Eranian <eranian@hpl.hp.com>
To: Ray Bryant <raybry@mpdtxmail.amd.com>
Cc: Andi Kleen <ak@suse.de>, discuss@x86-64.org, linux-kernel@vger.kernel.org,
       perfctr-devel@lists.sourceforge.net
Subject: Re: [Perfctr-devel] Re: Enabling RDPMC in user space by default
Message-ID: <20051129180903.GB6611@frankl.hpl.hp.com>
Reply-To: eranian@hpl.hp.com
References: <20051129151515.GG19515@wotan.suse.de> <200511291056.32455.raybry@mpdtxmail.amd.com>
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Andi,

On Tue, Nov 29, 2005 at 10:56:31AM -0600, Ray Bryant wrote:
> >
> > I'm considering to enable CR4.PCE by default on x86-64/i386. Currently it's
> > 0 which means RDPMC doesn't work. On x86-64 PMC 0 is always programmed to
> > be a cycle counter, so it would be useful to be able to access
> > this for measuring instructions. That's especially useful because RDTSC
> > does not necessarily count cycles in the current P state (already
> > the case on Intel CPUs and AMD's future direction seems to also
> > to decouple it from cycles) Drawback is that it stops during idle, but
> > that shouldn't be a big issue for normal measuring. It's not useful
> > as a real timer anyways.
> >

Where did you see that PMC0 (PERSEL0/PERFCTR0) can only be programmed
to count cpu cycles (i.e. cpu_clk_unhalted)? As far as I can tell from
the documentation, the 4 counters are symetrical and can measure
any event that the processor offers.

If you look at the perfmon x86-64 patch, you will see that under certain
circumstances, we enable CR4.pce. The main motivation is to alloc reading
counters at ring 3 with RDPMC. By default, CR4.pce must be cleared for
security reasons (covert channel). Perfmon only allows RDPMC for
self-monitoring threads or upon special request.

-- 
-Stephane
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