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[209.132.180.67]) by mx.google.com with ESMTP id y92si8161369plb.209.2019.07.05.02.09.28; Fri, 05 Jul 2019 02:09:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="bV5DgE/a"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728151AbfGEJI7 (ORCPT + 99 others); Fri, 5 Jul 2019 05:08:59 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:35713 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726116AbfGEJI6 (ORCPT ); Fri, 5 Jul 2019 05:08:58 -0400 Received: by mail-ed1-f65.google.com with SMTP id w20so7624342edd.2; Fri, 05 Jul 2019 02:08:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kSiMC23ISGGQqVJSQMfXoclzcfCXE9jKziQow8Aqu58=; b=bV5DgE/awiZCo70PJlZnyqIWgNigM3VnXItEoGqIjp2VwZAjg1Xtuv4hQpPEB0Jt6F Fq5BSo7B/rY4PMP/4Nwu27G69SQWZt+J6PAH2WXApCEy7ZPAb3tfWAIIP1vcjgWxUGlW eNQwjSrBPEfkUsBUD50OmCAvjzjhzwnTWIysIdTelYTQHmRPPTMScD6/trE7whDBf6HV G2WCWOFKxTlOoQwaIFS2Tr5i7U7WxlJCtJalVwHV9bXmlsNH/BVDB9FOg1yy7PB5xxRR H9Q5HcXpRB4X31oxQyBpicdAK4o0cRVRE8CevPbt2rFH5oT+MCW3xSEYts34UIcnBtz0 GbAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kSiMC23ISGGQqVJSQMfXoclzcfCXE9jKziQow8Aqu58=; b=JHHPGUKSpXxpFwYBds1FPWCCwK+2aq3Ggph5/1/HQAvPFPzB3qBnwRMoM0EAjPhQf6 oTyN3fEuUuXJul5RhFfohiIQRj/NwVxuHCfIcnzciwuKbo1CnWm/+jhZPnp3qqnL/70b fj+Mhg2ghHlEsAuAc+dsz+kYrCym7wDtIxdH/3Z/ti9nVHlWhvAWMlOBCu/DhgXzZd1r +vD+PM/C7Ram3ZUs6jAvbHbIQUDmLZlwEucmQcBGzwDzJzujDeSqVWq9QILdMFNGmFPB bxIMtXlvHyloBh5491/pmM+NGCe1g3YjTaQLhk9j4Dph6Ph0oIp3JNRIFDa5fJxOzcWI 4mHw== X-Gm-Message-State: APjAAAVHZoJdrNDHXvy62olkreQfsn95/LJ53GiDfeQMxl/DUFHAnQF9 XXgxWr5kG43loH2EDzlkdK7GNLRnPklTFHCK2Bg= X-Received: by 2002:a17:906:b7d8:: with SMTP id fy24mr2518380ejb.230.1562317736258; Fri, 05 Jul 2019 02:08:56 -0700 (PDT) MIME-Version: 1.0 References: <1561131532-14860-1-git-send-email-claudiu.manoil@nxp.com> <1561131532-14860-5-git-send-email-claudiu.manoil@nxp.com> <20190621164940.GL31306@lunn.ch> <20190624115558.GA5690@piout.net> <20190624142625.GR31306@lunn.ch> <20190624152344.3bv46jjhhygo6zwl@lx-anielsen.microsemi.net> <20190624162431.GX31306@lunn.ch> <20190624182614.GC5690@piout.net> <20190705044945.GA30115@lunn.ch> In-Reply-To: <20190705044945.GA30115@lunn.ch> From: Vladimir Oltean Date: Fri, 5 Jul 2019 12:08:45 +0300 Message-ID: Subject: Re: [PATCH net-next 4/6] arm64: dts: fsl: ls1028a: Add Felix switch port DT node To: Andrew Lunn Cc: Alexandre Belloni , "Allan W. Nielsen" , Claudiu Manoil , "David S . Miller" , "devicetree@vger.kernel.org" , "netdev@vger.kernel.org" , Alexandru Marginean , "linux-kernel@vger.kernel.org" , "UNGLinuxDriver@microchip.com" , Allan Nielsen , Rob Herring , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andrew, On Fri, 5 Jul 2019 at 07:49, Andrew Lunn wrote: > > Hi Vladimir > > > - DSA is typically used for discrete switches, switchdev is typically > > used for embedded ones. > > Typically DSA is for discrete switches, but not exclusively. The > b53/SF2 is embedded in a number of Broadcom SoCs. So this is no > different to Ocelot, except ARM vs MIPS. Also, i would disagree that > switchdev is used for embedded ones. Mellonex devices are discrete, on > a PCIe bus. I believe Netronome devices are also discrete PCIe > devices. In fact, i think ocelot is the only embedded switchdev > switch. > > So embedded vs discrete plays no role here at all. > drivers/staging/fsl-dpaa2/ethsw/ is another example of switchdev driver for an embedded switch. I would give it to you that the sample size is probably too small to say 'typically', but my point was that in order to support cascaded switches it makes more sense for those to be discrete. > > - The D in DSA is for cascaded switches. Apart from the absence of > > such a "Ocelot SoC" driver (which maybe can be written, I don't know), > > I think the switching core itself has some fundamental limitations > > that make a DSA implementation questionable: > > There is no requirement to implement D in DSA. In fact, only Marvell > does. None of the other switches do. And you will also find that most > boards with a Marvell switch use a single device. D in DSA is totally > optional. In fact, DSA is built from the ground up that nearly > everything is optional. Take a look at mv88e6060, as an example. It > implements nearly nothing. It cannot even offload a bridge to the > switch. > Let me see if I get your point. The D is optional, and the S is optional. So what's left? :) Also, there's a big difference between "the hardware can't do it" and "the driver doesn't implement it". If I follow your argument, would you write a DSA driver for a device that doesn't do L2 switching? Along that same line, what benefit does the DSA model bring to a switch that can't do cascading, compared to switchdev? I'm asking this as a user, not as a developer. > > So my conclusion is that DSA for Felix/Ocelot doesn't make a lot of > > sense if the whole purpose is to hide the CPU-facing netdev. > > You actually convinced me the exact opposite. You described the > headers which are needed to implement DSA. The switch sounds like it > can do what DSA requires. So DSA is the correct model. > > Andrew Somebody actually asked, with the intention of building a board, if it's possible to cascade the LS1028A embedded switch (Felix) with discrete SJA1105 devices - Felix being at the top of the switch tree. Does the DSA model support heterogeneous setups (parsing stacked headers)? I can't tell if that's how EDSA tags work. With switchdev for Felix there wouldn't be any problem - it just wouldn't be part of the DSA tree and its own driver would remove its tags before DSA would look at the rest. Regards, -Vladimir