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[209.132.180.67]) by mx.google.com with ESMTP id b13si17609160pgn.212.2019.07.08.01.47.18; Mon, 08 Jul 2019 01:47:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=F5M+QCqK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729145AbfGHG3H (ORCPT + 99 others); Mon, 8 Jul 2019 02:29:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:43850 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727052AbfGHG3H (ORCPT ); Mon, 8 Jul 2019 02:29:07 -0400 Received: from mail-vk1-f176.google.com (mail-vk1-f176.google.com [209.85.221.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E44CE2086C; Mon, 8 Jul 2019 06:29:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1562567346; bh=EzqBarqXMG3p46ZjfY0jADqQdj2XPJC8JYCsA8yVVSA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=F5M+QCqKjFW9AflXQMP3q35X2uuPfpHRrPvJWVdmnidBDNtTKcFC55JoM39gMM1EC 3XZ9NZ3ampyRu+4XoIHeDnV/AHXOpHEI8TC8c+Mbg5FotzV032G23wkJF8yjtri2dS TMhm8AA8i80B/2rlfOOlT/u589RqE+Q5KTnhME24= Received: by mail-vk1-f176.google.com with SMTP id 9so2248530vkw.4; Sun, 07 Jul 2019 23:29:05 -0700 (PDT) X-Gm-Message-State: APjAAAUhTPRUW8VPgn4EDzd5dH3Dw5cCseP88mErX5lkz0B4pwfF00uz a+zbFRgL0F0xvd1WALDEvD7qYNgRMZyEdAIlJc8= X-Received: by 2002:a1f:dec7:: with SMTP id v190mr979385vkg.39.1562567345067; Sun, 07 Jul 2019 23:29:05 -0700 (PDT) MIME-Version: 1.0 References: <20190705095726.21433-1-niklas.cassel@linaro.org> <20190705095726.21433-4-niklas.cassel@linaro.org> In-Reply-To: <20190705095726.21433-4-niklas.cassel@linaro.org> From: Ilia Lin Date: Mon, 8 Jul 2019 09:28:53 +0300 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 03/13] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional To: Niklas Cassel Cc: Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Ilia Lin On Fri, Jul 5, 2019 at 12:58 PM Niklas Cassel wrote: > > Not all Qualcomm platforms need to care about the speedbin efuse, > nor the value blown into the speedbin efuse. > Therefore, make the nvmem-cells and opp-supported-hw properties > optional. > > Signed-off-by: Niklas Cassel > --- > Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt > index 198441e80ba8..c5ea8b90e35d 100644 > --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt > +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt > @@ -20,6 +20,10 @@ In 'cpus' nodes: > In 'operating-points-v2' table: > - compatible: Should be > - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. > + > +Optional properties: > +-------------------- > +In 'operating-points-v2' table: > - nvmem-cells: A phandle pointing to a nvmem-cells node representing the > efuse registers that has information about the > speedbin that is used to select the right frequency/voltage > -- > 2.21.0 >