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[209.132.180.67]) by mx.google.com with ESMTP id f1si17353863pjw.100.2019.07.08.05.34.35; Mon, 08 Jul 2019 05:34:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XNBc9Ibt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728758AbfGHIuC (ORCPT + 99 others); Mon, 8 Jul 2019 04:50:02 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:46151 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728011AbfGHIuC (ORCPT ); Mon, 8 Jul 2019 04:50:02 -0400 Received: by mail-pf1-f195.google.com with SMTP id c73so2585658pfb.13 for ; Mon, 08 Jul 2019 01:50:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0f8cjmK92HlNgqdiIijajGEwI8ww5eZP9m3oc7p56Nc=; b=XNBc9Ibt2RD9ZScjtlSg3q03aKcjt0mkX8Tnqlq8ia3SlJkvgZLuf6bCf81oDV0c3g mh6NaGDyDwg2iBHEvtwDBdVmHb5o9isAOZ3qTc5cvLFw2fx41/9zqBIhamXiWOuk+auA 2o0a+Vn5joLTl6S0zcEwQCZxvb0Ajiddc9J7o9f+U5KWykYYg+m4dNkDfKlSttULO4Gy c0Og20/SbiF75xz6+y08B+exkdUkdAa/17gaxv1zKVDFpyu/MGrVei5O9Kj2MG8Bw7Zt QFIizNqncdaiFzzHW12Xr172RlniGm1Ev8NfQHPgWZ4xYEiLO5SZ4M/CT/kCW9RNQDfB /ksQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0f8cjmK92HlNgqdiIijajGEwI8ww5eZP9m3oc7p56Nc=; b=OLSq0mqFHy7ZCO0FqF6efEmHWACILRhBg5iZ6EXFCUcJdP0J8LUdBU10vF5Sr/yL5x WzKo7Lm3S/uafnW10fXOTa0mY4DiEIc5oNWVl1SYdszua1L/ZbkXNPFYJDuvLKFbNPBw 5g3QD+GofgypxK1T7VRy5aYcMMRJbKdN4W11YczAa7cdIjkVDCXAz9iKpSEKr1CuY4nF nzut+HKuoDwvHlBK/L35tk88hP4vSvw+Nj4YgaxwKLDCVGt+DRjogevzK3vw0/u/jmcV 4hUOJrM6aDygRQVPmN7timBGKmgX4cu9lcIZoZQDLanv52wfWvoexhYB77HpYu+Xo/m2 OLzA== X-Gm-Message-State: APjAAAVMW6C1JapycenMW8EOvom5wBBtkFVFTpyhlfVB6Yqt7XAD/Pu7 TsAWOcrsUEN5iBcFVUi9+2EQCg== X-Received: by 2002:a17:90a:2023:: with SMTP id n32mr22686652pjc.3.1562575801326; Mon, 08 Jul 2019 01:50:01 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id t17sm18436886pgg.48.2019.07.08.01.50.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Jul 2019 01:50:00 -0700 (PDT) Date: Mon, 8 Jul 2019 14:19:57 +0530 From: Viresh Kumar To: Anson Huang Cc: Leonard Crestez , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , Jacky Bai , Daniel Baluta , "l.stach@pengutronix.de" , Abel Vesa , "andrew.smirnov@gmail.com" , "ccaione@baylibre.com" , "angus@akkea.ca" , "agx@sigxcpu.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , dl-linux-imx Subject: Re: [PATCH 2/2] arm64: dts: imx8mm: Assign highest opp as suspend opp Message-ID: <20190708084957.waiwdun327pgvfv4@vireshk-i7> References: <20190704061403.8249-1-Anson.Huang@nxp.com> <20190704061403.8249-2-Anson.Huang@nxp.com> <20190708082511.py7gnjbqyp7bnhqx@vireshk-i7> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716-391-311a52 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08-07-19, 08:43, Anson Huang wrote: > Hi, Viresh > > > On 04-07-19, 07:49, Leonard Crestez wrote: > > > On 7/4/2019 9:23 AM, Anson.Huang@nxp.com wrote: > > > > From: Anson Huang > > > > > > > > Assign highest OPP as suspend OPP to reduce suspend/resume latency > > > > on i.MX8MM. > > > > > > > > Signed-off-by: Anson Huang > > > > --- > > > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > > index b11fc5e..3a62407 100644 > > > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > > @@ -136,6 +136,7 @@ > > > > opp-microvolt = <1000000>; > > > > opp-supported-hw = <0x8>, <0x3>; > > > > clock-latency-ns = <150000>; > > > > + opp-suspend; > > > > }; > > > > }; > > > > > > What if the highest OPP is unavailable due to speed grading? > > > > What does this exactly mean ? How is the OPP made unavailable in your > > case ? > > That is because in i.MX8M series SoCs, the speed grading and market segment > fuses settings could affect the OPP defined in DT, in a word, all possible OPPs > are defined in DT, but each parts could ONLY select some of them to be working > OPPs, so if the "opp-suspend" is added for 1 OPP in DT, if the part's speed grading or > market segment fuse settings make that OPP as unavailable, then that "opp-suspend" > is NOT working at all. How is this selection done ? You using some OPP helper or something else ? -- viresh