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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id q1sm32442857pfn.178.2019.07.08.17.57.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Jul 2019 17:57:40 -0700 (PDT) Date: Mon, 8 Jul 2019 17:58:10 -0700 From: Nicolin Chen To: "S.j. Wang" Cc: "timur@kernel.org" , "Xiubo.Lee@gmail.com" , "festevam@gmail.com" , "broonie@kernel.org" , "alsa-devel@alsa-project.org" , "linuxppc-dev@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH V2 2/2] ASoC: fsl_esai: recover the channel swap after xrun Message-ID: <20190709005809.GA28003@Asurada-Nvidia.nvidia.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 05, 2019 at 07:03:47AM +0000, S.j. Wang wrote: > > > > > + > > > + /* restore registers by regcache_sync */ > > > + fsl_esai_register_restore(esai_priv); > > > + > > > + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, > > > + ESAI_xCR_xPR_MASK, 0); > > > + regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, > > > + ESAI_xCR_xPR_MASK, 0); > > > > And just for curious, can (or shall) we stuff this personal reset to the reset() > > function? I found this one is a part of the reset routine being mentioned in > > the RM -- it was done after ESAI reset is done via ECR register. > > > > There is a problem to do this, TPR/RPR need to be clear after configure the control > register. (TCCR, TCR). So it seems not only one place (reset function) need to be > changed. Do you know (or remember) why we suddenly involve this TPR/PRP? The driver has no problem so far, even if we don't have them. The "personal reset" sounds like a feature that we would use to reset TX or RX individually, while this hw_reset() does a full reset for both TX and RX. So I wonder whether they're necessary.