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([2001:b07:6468:f312:19db:ad53:90ea:9423]) by smtp.gmail.com with ESMTPSA id n1sm910730wrx.39.2019.07.09.23.20.36 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Tue, 09 Jul 2019 23:20:37 -0700 (PDT) Subject: Re: [RFC PATCH] x86: Remove X86_FEATURE_MFENCE_RDTSC To: "Lendacky, Thomas" , Josh Poimboeuf , "x86@kernel.org" Cc: "linux-kernel@vger.kernel.org" , Andrew Cooper , Thomas Gleixner , Pu Wen , Borislav Petkov References: <45f247d2-80f5-6c8c-d11e-965a3da8a88f@amd.com> From: Paolo Bonzini Message-ID: <4a13c6a3-a13e-d3e5-0008-41a6d47a6eff@redhat.com> Date: Wed, 10 Jul 2019 08:20:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <45f247d2-80f5-6c8c-d11e-965a3da8a88f@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/07/19 21:32, Lendacky, Thomas wrote: >> AMD and Intel both have serializing lfence (X86_FEATURE_LFENCE_RDTSC). >> They've both had it for a long time, and AMD has had it enabled in Linux >> since Spectre v1 was announced. >> >> Back then, there was a proposal to remove the serializing mfence feature >> bit (X86_FEATURE_MFENCE_RDTSC), since both AMD and Intel have >> serializing lfence. At the time, it was (ahem) speculated that some >> hypervisors might not yet support its removal, so it remained for the >> time being. >> >> Now a year-and-a-half later, it should be safe to remove. > > I vaguely remember a concern from a migration point of view, maybe? Adding > Paolo to see if he has any concerns. It would be a problem to remove the conditional "if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))" from svm_get_msr_feature. But removing support for X86_FEATURE_MFENCE_RDTSC essentially amounts to removing support for hypervisors that haven't been updated pre-Spectre. That's fair enough, I think. Paolo