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Subject: Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64
To:     Maran Wilson <maran.wilson@oracle.com>,
        James Morse <james.morse@arm.com>,
        Xiongfeng Wang <wangxiongfeng2@huawei.com>
Cc:     guohanjun@huawei.com, john.garry@huawei.com, rjw@rjwysocki.net,
        linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
        huawei.libin@huawei.com, jonathan.cameron@huawei.com,
        kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
References: <1561776155-38975-1-git-send-email-wangxiongfeng2@huawei.com>
 <82879258-46a7-a6e9-ee54-fc3692c1cdc3@arm.com>
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From:   Marc Zyngier <marc.zyngier@arm.com>
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Organization: ARM Ltd
Message-ID: <06ef13e1-fffe-d4a2-721e-f666f331fb3c@arm.com>
Date:   Wed, 10 Jul 2019 10:15:05 +0100
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Sender: linux-kernel-owner@vger.kernel.org
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On 09/07/2019 20:06, Maran Wilson wrote:
> On 7/5/2019 3:12 AM, James Morse wrote:
>> Hi guys,
>>
>> (CC: +kvmarm list)
>>
>> On 29/06/2019 03:42, Xiongfeng Wang wrote:
>>> This patchset mark all the GICC node in MADT as possible CPUs even though it
>>> is disabled. But only those enabled GICC node are marked as present CPUs.
>>> So that kernel will initialize some CPU related data structure in advance before
>>> the CPU is actually hot added into the system. This patchset also implement
>>> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are
>>> needed to enable CPU hotplug.
>>>
>>> To support CPU hotplug, we need to add all the possible GICC node in MADT
>>> including those CPUs that are not present but may be hot added later. Those
>>> CPUs are marked as disabled in GICC nodes.
>> ... what do you need this for?
>>
>> (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to
>> the platform, we usually mean taking CPUs online/offline for power management. e.g.
>> cpuhp_offline_cpu_device())
>>
>> It looks like you're adding support for hot-adding a new package/die to the platform ...
>> but only for virtualisation.
>>
>> I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know
>> these vcpu exist before you can enter the guest for the first time. You can't create them
>> late. At best you're saving the host scheduling a vcpu that is offline. Is this really a
>> problem?
>>
>> If we moved PSCI support to user-space, you could avoid creating host vcpu threads until
>> the guest brings the vcpu online, which would solve that problem, and save the host
>> resources for the thread too. (and its acpi/dt agnostic)
>>
>> I don't see the difference here between booting the guest with 'maxcpus=1', and bringing
>> the vcpu online later. The only real difference seems to be moving the can-be-online
>> policy into the hypervisor/VMM...
> 
> Isn't that an important distinction from a cloud service provider's 
> perspective?
> 
> As far as I understand it, you also need CPU hotplug capabilities to 
> support things like Kata runtime under Kubernetes. i.e. when 
> implementing your containers in the form of light weight VMs for the 
> additional security ... and the orchestration layer cannot determine 
> ahead of time how much CPU/memory resources are going to be needed to 
> run the pod(s).

Why would it be any different? You can pre-allocate your vcpus, leave
them parked until some external agent decides to signal the container
that it it can use another bunch of CPUs. At that point, the container
must actively boot these vcpus (they aren't going to come up by magic).

Given that you must have sized your virtual platform to deal with the
maximum set of resources you anticipate (think of the GIC
redistributors, for example), I really wonder what you gain here.

> 
> Thanks,
> -Maran
> 
>>
>> I think physical package/die hotadd is a much bigger, uglier problem than doing the same
>> under virtualisation. Its best to do this on real hardware first so we don't miss
>> something. (cpu-topology, numa, memory, errata, timers?)
>> I'm worried that doing virtualisation first means the firmware-requirements for physical
>> hotadd stuff is "whatever Qemu does".

For sure, I want to model the virtualization side after the actual HW,
and not the other way around. Live reconfiguration of the interrupt
topology (and thus the whole memory map) will certainly be challenging.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...