Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   "Phillips, Kim" <kim.phillips@amd.com>
To:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
        "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bp@alien8.de" <bp@alien8.de>
Subject: Re: [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for
 chip selects handling
Thread-Topic: [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for
 chip selects handling
Thread-Index: AQHVN0Asc2CazzfP60GUzjiUo3pGLA==
Date:   Wed, 10 Jul 2019 16:54:44 +0000
Message-ID: <af8c4e5e-d1c1-b733-9303-014314aec9d5@amd.com>
References: <20190709215643.171078-1-Yazen.Ghannam@amd.com>
 <20190709215643.171078-2-Yazen.Ghannam@amd.com>
In-Reply-To: <20190709215643.171078-2-Yazen.Ghannam@amd.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-originating-ip: [165.204.77.1]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: 9ede45b6-e7f9-4a75-9786-08d705574f45
x-ms-office365-filtering-ht: Tenant
x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:MWHPR12MB1758;
x-ms-traffictypediagnostic: MWHPR12MB1758:
x-microsoft-antispam-prvs: <MWHPR12MB1758EF86B2D73DFBD857034087F00@MWHPR12MB1758.namprd12.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:1824;
x-forefront-prvs: 0094E3478A
x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(396003)(136003)(376002)(366004)(39860400002)(199004)(189003)(3846002)(14454004)(8676002)(6486002)(6436002)(6116002)(52116002)(2501003)(8936002)(4326008)(26005)(5660300002)(2906002)(25786009)(256004)(6246003)(53936002)(66446008)(76176011)(64756008)(31696002)(66476007)(66556008)(229853002)(66946007)(81156014)(81166006)(6512007)(186003)(66066001)(54906003)(86362001)(110136005)(71200400001)(71190400001)(31686004)(478600001)(102836004)(486006)(316002)(305945005)(7736002)(446003)(11346002)(68736007)(386003)(53546011)(6506007)(36756003)(476003)(2616005)(99286004);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHPR12MB1758;H:MWHPR12MB1806.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1;
received-spf: None (protection.outlook.com: amd.com does not designate
 permitted sender hosts)
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam-message-info: Pa9J3ZWM7CjaBIbDGWuKpDyvncEQouLtqDtBEhf/P35JRP0TpxAeMFymNO1cil0yQ2QQSSHOPnz9XGUgQEfFIddRiZywWnmFjPHxa00Lz12pOEvQ80HqdvF2Yp+hdaOj7pUlQy7VaselJczAiXFBL8Stxi/fk/xhIyjthTxqXZ0dkLWAFtH5duC3v/9r8vgAS35jRaUQR5Cx+tlvFrjBMLs8tBQjSQI6SHh9UwC46lJJk/w7m3B3wyR6NWVBj0D4xIKAS6LTAP9LvIXf67Lwx/W64LFjXlgPua5O8AFfnm62c8wxjeEjzyOSYicFmRVIIFUpiMDKlzXwNkl/b1fqrlmLzVyKMQinYGg3Cj7IujZRr1RwKVYOmr7nPfpSkLuacNtTmrd9U9Crrq4AD5ArbE6WlPatfoe6GUPkrKmQaFM=
Content-Type: text/plain; charset="Windows-1252"
Content-ID: <5B6D0F510AADE5429747A14E82A53C05@namprd12.prod.outlook.com>
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 9ede45b6-e7f9-4a75-9786-08d705574f45
X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 16:54:44.8840
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: kphillips@amd.com
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1758
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 7/9/19 4:56 PM, Ghannam, Yazen wrote:
> From: Yazen Ghannam <yazen.ghannam@amd.com>
>=20
> The struct chip_select array that's used for saving chip select bases
> and masks is fixed at length of two. There should be one struct
> chip_select for each controller, so this array should be increased to
> support systems that may have more than two controllers.
>=20
> Increase the size of the struct chip_select array to eight, which is the
> largest number of controllers per die currently supported on AMD
> systems.
>=20
> Fix number of DIMMs and Chip Select bases/masks on Family17h, because AMD
> Family 17h systems support 2 DIMMs, 4 CS bases, and 2 CS masks per
> channel.
>=20
> Also, carve out the Family 17h+ reading of the bases/masks into a
> separate function. This effectively reverts the original bases/masks
> reading code to before Family 17h support was added.
>=20
> This is a second version of a commit that was reverted.
>=20
> Fixes: 07ed82ef93d6 ("EDAC, amd64: Add Fam17h debug output")
> Fixes: 8de9930a4618 ("Revert "EDAC/amd64: Support more than two controlle=
rs for chip select handling"")
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---

For this and the rest of the series:

Tested-by: Kim Phillips <kim.phillips@amd.com>

Thanks,

Kim