Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp10632360ybi; Thu, 11 Jul 2019 08:26:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqzOYOF18FsoEfLSzEpiQfX1YmVF5sXIzh/DOqCRXz59Odav1u9an0PXvDbed6WZOjOQS4y/ X-Received: by 2002:a63:6056:: with SMTP id u83mr2131941pgb.181.1562858784469; Thu, 11 Jul 2019 08:26:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562858784; cv=none; d=google.com; s=arc-20160816; b=LXFiB5aLEWKh2e1CdnPV2cT+yGP+5/4p4M28j8jF2uQe9Lv1HmEsLrMvOAYVTllQGu PwTgTgBOAfV8I4sAgIIBaYGIXR72fGW9PePiQcRVW1RNaGU5YQFYXluq97GWAqYzqJK5 OJMM55T2C7XHTS3EOpUCsLA8lnV8Cf3VOHlJEpmm1JFw3CAVAjZSTjM/gAHbbvHRQErv kJzfTJX7vKxvodksv1yPvLO7ZMwn+JappF2xP+6TSI5PCrSF7KJfaWqRmUeK/ZH8/LXh HBMWxDEy3gcOYdeFDoTL0CZnf0MAOTVhhLn/OtbNT+JaNfMeI4CpborSEDitl34TTy9T /8Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:dkim-signature; bh=+HlbWEQmRduQNmwZFRzhfjm5S2Nl7jUTbuTLfBpBQqk=; b=jnbefJQZCHoetzPKXppIICQq9N0EwTnwukc41nlCtHSck4bXqsp1M3B0hkB+bfhg00 NbAwPIAbneYRfiPoR4+2FCyuJSajZqEMOJCHD3wfddk4RUY7+1BqiE8u+ZGheUlP5r26 TKpk2IXjwCy4xfM2oNBxoaqcRXf3tilKj27X9gScs40X5iP7HZ4oJ+imwWp8CVRAg10j aTL3Ytex8bKpbP5X8rgMCd0dBC6axtADKrFW+WjewtPZwqYHnSgHTv0eFcfAmx2axUx4 5BdsTBpCKql9ODTTOSB3ND1CmpTi4UCCU3XEPfkaOOgqVQY0QtGTOq4xrcr22+iE/QyI 6R9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sirena.org.uk header.s=20170815-heliosphere header.b="Wou5o/MP"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u3si5180763plz.201.2019.07.11.08.26.09; Thu, 11 Jul 2019 08:26:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@sirena.org.uk header.s=20170815-heliosphere header.b="Wou5o/MP"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728772AbfGKOmK (ORCPT + 99 others); Thu, 11 Jul 2019 10:42:10 -0400 Received: from heliosphere.sirena.org.uk ([172.104.155.198]:51056 "EHLO heliosphere.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728678AbfGKOmK (ORCPT ); Thu, 11 Jul 2019 10:42:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=+HlbWEQmRduQNmwZFRzhfjm5S2Nl7jUTbuTLfBpBQqk=; b=Wou5o/MPpOc6TgukRzTBE/GH+ RjTTLTQbUoZs3rqtFDNYiTTqcywlE97WS1aQvfu0aZSweV6wT+FTGnPpwgRC7hPVC1T1yktQXgFF0 y4n54l2AWJtFqwvW014NATDZc/TT5iZI6BS4La50RlA2uClTaigHVREvsuAgme/SIif/I=; Received: from [217.140.106.52] (helo=fitzroy.sirena.org.uk) by heliosphere.sirena.org.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1hlaGm-0002Ug-9P; Thu, 11 Jul 2019 14:42:00 +0000 Received: by fitzroy.sirena.org.uk (Postfix, from userid 1000) id 7990FD02DA8; Thu, 11 Jul 2019 15:41:59 +0100 (BST) Date: Thu, 11 Jul 2019 15:41:59 +0100 From: Mark Brown To: Jeffrey Hugo Cc: Andrzej Hajda , Laurent Pinchart , Dave Airlie , Daniel Vetter , Rob Clark , Bjorn Andersson , "open list:DRM PANEL DRIVERS" , MSM , lkml Subject: Re: [PATCH 1/2] regmap: Add DSI bus support Message-ID: <20190711144159.GH14859@sirena.co.uk> References: <20190703214326.41269-1-jeffrey.l.hugo@gmail.com> <20190703214512.41319-1-jeffrey.l.hugo@gmail.com> <20190706010604.GG20625@sirena.org.uk> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="aF3LVLvitz/VQU3c" Content-Disposition: inline In-Reply-To: X-Cookie: Visit beautiful Vergas, Minnesota. User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --aF3LVLvitz/VQU3c Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jul 10, 2019 at 12:08:34PM -0600, Jeffrey Hugo wrote: > On Fri, Jul 5, 2019 at 7:06 PM Mark Brown wrote: > The addresses for these spec defined messages are 8-bit wide, so 256 > valid "destinations". However, the payload is variable. Most of the > defined operations take an 8-bit payload, but there are a few that I > see with 16-bit payloads. Oh, good, variable register sizes, what a market leading idea :( That basically doesn't work with regmap, you need to either define one regmap per register size and attach them to the device or use reg_read() and reg_write() and hide the complexity in there. > As the contents of the generic read/write messages are implementation > defined, the answer to your question seems to be no - the spec does > not define that the registers are 8-bit addressable, and 8-bit wide. The code definitely ought to at least be more flexible then. Right now it's very hard coded. > I think perhaps the discussion needs to step back a bit, and decide > how flexible do we want this regmap over DSI to be? I think its > usefulness comes from when a device can be configured via multiple > interfaces, so I don't expect it to be useful for every DSI interface. > It seems like the DSI panels use DSI directly to craft their > configuration. As a result, we are probably looking at just devices > which use the generic read/write commands, but sadly the format for > those is not universal per the spec. From the implementations I've > seen, I suspect 8-bit addressing of 8-bit wide registers to be the > most common, but apparently there is an exception to that already in > the one device that I care about. It's relatively easy to add a bunch of special cases in - look at how the I2C code handles it, keying off a combination of the register configuration and the capabilities of the host controller. I guess for this it'd mainly be the register configuration. You might find the reg_read()/reg_write() interface better than the raw buffer one for some of the formats, it does let=20 > Do we want to go forward with this regmap support just for the one TI > device, and see what other usecases come out of it, and attempt to > solve those as we go? I have no strong opinions here, it looks fine from a framework point of view though it's unclear to me if viewing it as a register map meshes well with how the hardware is designed or not - it seems plausible though. --aF3LVLvitz/VQU3c Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAl0nSrQACgkQJNaLcl1U h9Dqygf/XOpd88JPRHZWBN+yYZ3UHJfhBe6xy8/HfJBBT8sXXA2L3k7rHpRMmhKk RC58a6kuy8mDm+tQhIgEwHUlFotAHGk8kn0yNQuVK0XNL4zvAqdcQHV+gsn//x6G R3PQrLboonlT69lWDNW4dI1zc78mY6FzKQRtFa7kmIYZ5hr/WwtR9TfpReeUxLCr P5FYi4QzBp3uloWecgLExYmFZj3IHznUWpp8Hm11JDXyrpVShOMJCiA99q/W9N6A ALxrijQlTenDH7gMw7YEaDhnl+osCa392CguDJiSNbDW7usZ+5WGOF7TGOLu8F+u udGDeMVl9eOc7g2CHoRTEg6/WtQv/A== =1lgs -----END PGP SIGNATURE----- --aF3LVLvitz/VQU3c--