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From:   Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>
CC:     Lihua Yao <Lihua.Yao@desay-svautomotive.com>,
        Wolfram Sang <wsa+renesas@sang-engineering.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Hien Dang <hien.dang.eb@renesas.com>,
        Linh Phung <linh.phung.jy@renesas.com>
Subject: RE: [PATCH] clk: renesas: cpg-mssr: Fix reset control race condition
Thread-Topic: [PATCH] clk: renesas: cpg-mssr: Fix reset control race condition
Thread-Index: AQHVN+khR8N/7lmi1E2fDohgjmSMGabGsnwg
Date:   Fri, 12 Jul 2019 09:19:47 +0000
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References: <20190711130359.1060-1-geert+renesas@glider.be>
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Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Thursday, July 11, 2019 10:04 PM
>=20
> The module reset code in the Renesas CPG/MSSR driver uses
> read-modify-write (RMW) operations to write to a Software Reset Register
> (SRCRn), and simple writes to write to a Software Reset Clearing
> Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
> User's Manuals.
>=20
> However, this may cause a race condition when two devices are reset in
> parallel: if the reset for device A completes in the middle of the RMW
> operation for device B, device A may be reset again, causing subtle
> failures (e.g. i2c timeouts):
>=20
> 	thread A			thread B
> 	--------			--------
>=20
> 	val =3D SRCRn
> 	val |=3D bit A
> 	SRCRn =3D val
>=20
> 	delay
>=20
> 					val =3D SRCRn (bit A is set)
>=20
> 	SRSTCLRn =3D bit A
> 	(bit A in SRCRn is cleared)
>=20
> 					val |=3D bit B
> 					SRCRn =3D val (bit A and B are set)
>=20
> This can be reproduced on e.g. Salvator-XS using:
>=20
>     $ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done &
>     $ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done &
>=20
>     i2c-rcar e6510000.i2c: error -110 : 40000002
>     i2c-rcar e66d8000.i2c: error -110 : 40000002
>=20
> According to the R-Car Gen3 Hardware Manual Errata for Rev.
> 0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware
> User's Manual, writes to SRCRn do not require read-modify-write cycles.
>=20
> Note that the R-Car Gen2 Hardware User's Manual has not been updated
> yet, and still says a read-modify-write sequence is required.  According
> to the hardware team, the reset hardware block is the same on both R-Car
> Gen2 and Gen3, though.
>=20
> Hence fix the issue by replacing the read-modify-write operations on
> SRCRn by simple writes.
>=20
> Reported-by: Yao Lihua <Lihua.Yao@desay-svautomotive.com>
> Fixes: 6197aa65c4905532 ("clk: renesas: cpg-mssr: Add support for reset c=
ontrol")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---

Thank you for the patch! Our test team tested this patch, so

Tested-by: Linh Phung <linh.phung.jy@renesas.com>

> So far I haven't been able to reproduce the issue on R-Car Gen2 (after
> forcing i2c reset on Gen2, too).  Perhaps my Koelsch doesn't have enough
> CPU cores.  What about Lager?

According to the test team, Lager also could not reproduce this issue.
Should we investigate it why?

Best regards,
Yoshihiro Shimoda

> Hi Mike, Stephen,
>=20
> As this is a bugfix, can you please take this directly, if accepted?
>=20
> Thanks!
> ---
>  drivers/clk/renesas/renesas-cpg-mssr.c | 16 ++--------------
>  1 file changed, 2 insertions(+), 14 deletions(-)
>=20
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas=
/renesas-cpg-mssr.c
> index 52bbb9ce3807db31..d4075b13067429cd 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -572,17 +572,11 @@ static int cpg_mssr_reset(struct reset_controller_d=
ev *rcdev,
>  	unsigned int reg =3D id / 32;
>  	unsigned int bit =3D id % 32;
>  	u32 bitmask =3D BIT(bit);
> -	unsigned long flags;
> -	u32 value;
>=20
>  	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
>=20
>  	/* Reset module */
> -	spin_lock_irqsave(&priv->rmw_lock, flags);
> -	value =3D readl(priv->base + SRCR(reg));
> -	value |=3D bitmask;
> -	writel(value, priv->base + SRCR(reg));
> -	spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +	writel(bitmask, priv->base + SRCR(reg));
>=20
>  	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
>  	udelay(35);
> @@ -599,16 +593,10 @@ static int cpg_mssr_assert(struct reset_controller_=
dev *rcdev, unsigned long id)
>  	unsigned int reg =3D id / 32;
>  	unsigned int bit =3D id % 32;
>  	u32 bitmask =3D BIT(bit);
> -	unsigned long flags;
> -	u32 value;
>=20
>  	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
>=20
> -	spin_lock_irqsave(&priv->rmw_lock, flags);
> -	value =3D readl(priv->base + SRCR(reg));
> -	value |=3D bitmask;
> -	writel(value, priv->base + SRCR(reg));
> -	spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +	writel(bitmask, priv->base + SRCR(reg));
>  	return 0;
>  }
>=20
> --
> 2.17.1