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From:   Andy Lutomirski <luto@amacapital.net>
Date:   Mon, 15 Jul 2019 07:31:23 -0700
Message-ID: <CALCETrXQaayeV-6n_2dycMo7ienQPizTqYQDEAy1C2KLPrCt8Q@mail.gmail.com>
Subject: Re: [PATCH] x86/cpu/intel: Skip CPA cache flush on CPUs with cache self-snooping
To:     Uros Bizjak <ubizjak@gmail.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Peter Zijlstra <peterz@infradead.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>, X86 ML <x86@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Mon, Jul 15, 2019 at 7:21 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> CPUs which have self-snooping capability can handle conflicting
> memory type across CPUs by snooping its own cache. Commit #fd329f276ecaa
> ("x86/mtrr: Skip cache flushes on CPUs with cache self-snooping")
> avoids cache flushes when MTRR registers are programmed. The Page
> Attribute Table (PAT) is a companion feature to the MTRRs, and according
> to section 11.12.4 of the Intel 64 and IA 32 Architectures Software
> Developer's Manual, if the CPU supports cache self-snooping, it is not
> necessary to flush caches when remapping a page that was previously
> mapped as a different memory type.
>
> Note that commit #1e03bff360010
> ("x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata")
> cleared cache self-snoop capability for CPUs where conflicting memory types
> lead to unpredictable behavior, machine check errors, or hangs.

It looks like this won't affect the SEV code paths, so I'm not
thinking of anything that this will break.  But Dave and Peter are
much, much more familiar with the messes this could cause than I am.

--Andy