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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss Subject: RE: [PATCHv3 0/6] CPPC optional registers AMD support Thread-Topic: [PATCHv3 0/6] CPPC optional registers AMD support Thread-Index: AQHVN057bBT6zB/KfUWS9uFb7V9o2qbIYcuAgAOQCkA= Date: Mon, 15 Jul 2019 17:57:16 +0000 Message-ID: References: <20190713104619.GA3496@hirez.programming.kicks-ass.net> In-Reply-To: <20190713104619.GA3496@hirez.programming.kicks-ass.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; x-originating-ip: [2601:3c2:8280:2327:3414:3059:320b:d027] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 7ae91538-868a-4271-bb19-08d7094ddfd9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2782; x-ms-traffictypediagnostic: SN6PR12MB2782: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7219; x-forefront-prvs: 00997889E7 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(376002)(396003)(366004)(136003)(39860400002)(189003)(199004)(13464003)(9686003)(52536014)(6636002)(446003)(316002)(476003)(66556008)(6246003)(66476007)(229853002)(8676002)(64756008)(53936002)(55016002)(46003)(66446008)(66946007)(478600001)(74316002)(102836004)(76176011)(76116006)(14454004)(5660300002)(71190400001)(6436002)(99286004)(4326008)(7696005)(53546011)(305945005)(6506007)(7736002)(33656002)(8936002)(256004)(14444005)(86362001)(6116002)(81166006)(486006)(81156014)(186003)(71200400001)(54906003)(11346002)(2906002)(110136005)(25786009)(68736007)(7416002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2782;H:SN6PR12MB2639.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: fRJjb1JvjW3xJdodAtXkzcpGZnc85cpzTeDCvr/x5qebuU08nIgHJBB8R42I0cstTXKDBnDoRu6xJYDWsFFsdpZoUeKjnAc2/7COCs7n7lsVoAbWLL55iAREdGMjgupV20lhIz+iFiOKe5OOmbjzc/HCtSbiiWIAuiUtAV52KRB0BM2++VgsLHujLtm6uGiCb+BY0QxE90xCP2PXZ02XbhDI1BlqRa9C77hCxfwJbsncLe2t5SGswXXYXHNtvXRYA3F/PVvmvjPmd4fiCZo6wacJzXodoFAy1phRFkIVIQ00LWpDcaelRhgSj840HBwotCCUC/lIVmJ76JELGWBx7CAVkfrqaBD/xgs3YLAyvborXx24RLsYAn6zzFnP3/beqVBske+s2aU2kL44FaRV1Mj9s0QQHWZj1EmIZIK+1lA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7ae91538-868a-4271-bb19-08d7094ddfd9 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jul 2019 17:57:16.7745 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yghannam@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2782 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Peter Zijlstra > Sent: Saturday, July 13, 2019 5:46 AM > To: Natarajan, Janakarajan > Cc: linux-acpi@vger.kernel.org; linux-kernel@vger.kernel.org; linux-pm@vg= er.kernel.org; devel@acpica.org; Rafael J . Wysocki > ; Len Brown ; Viresh Kumar ; Robert Moore > ; Erik Schmauss ; Ghanna= m, Yazen > Subject: Re: [PATCHv3 0/6] CPPC optional registers AMD support >=20 > On Wed, Jul 10, 2019 at 06:37:09PM +0000, Natarajan, Janakarajan wrote: > > CPPC (Collaborative Processor Performance Control) offers optional > > registers which can be used to tune the system based on energy and/or > > performance requirements. > > > > Newer AMD processors (>=3D Family 17h) add support for a subset of thes= e > > optional CPPC registers, based on ACPI v6.1. > > > > The following are the supported CPPC registers for which sysfs entries > > are created: > > * enable (NEW) > > * max_perf (NEW) > > * min_perf (NEW) > > * energy_perf > > * lowest_perf > > * nominal_perf > > * desired_perf (NEW) > > * feedback_ctrs > > * auto_sel_enable (NEW) > > * lowest_nonlinear_perf > > > > First, update cppc_acpi to create sysfs entries only when the optional > > registers are known to be supported. > > > > Next, a new CPUFreq driver is introduced to enable the OSPM and the use= rspace > > to access the newly supported registers through sysfs entries found in > > /sys/devices/system/cpu/cpu/amd_cpufreq/. > > > > This new CPUFreq driver can only be used by providing a module paramete= r, > > amd_cpufreq.cppc_enable=3D1. > > > > The purpose of exposing the registers via the amd-cpufreq sysfs entries= is to > > allow the userspace to: > > * Tweak the values to fit its workload. > > * Apply a profile from AMD's optimization guides. >=20 > So in general I think it is a huge mistake to expose all that to > userspace. Before you know it, there's tools that actually rely on it, > and then inhibit the kernel from doing anything sane with it. >=20 Okay, makes sense. Is there any way to expose a sysfs interface and make it explicitly "experi= mental"? Maybe putting it in Documentation/ABI/testing/? Or do you think it's just not worth it? > > Profiles will be documented in the performance/optimization guides. >=20 > I don't think userspace can really do anything sane with this; it lacks > much if not all useful information. >=20 > > Note: > > * AMD systems will not have a policy applied in the kernel at this time= . >=20 > And why the heck not? We're trying to move all cpufreq into the > scheduler and have only a single governor, namely schedutil -- yes, > we're still stuck with legacy, and we're still working on performance > parity in some cases, but I really hope to get rid of all other cpufreq > governors eventually. >=20 Because this is new to AMD systems, we didn't want to enforce a default pol= icy. We figured that exposing the CPPC interface would be a good way to decouple= policy from the kernel and let users experiment/tune their systems, like u= sing the userspace governor. And if some pattern emerged then we could make= that a default policy in the kernel (for AMD or in general). But you're saying we should focus more on working with the schedutil govern= or, correct? Do you think there's still a use for a userspace governor? > And if you look at schedutil (schedutil_cpu_util in specific) then > you'll see it is already prepared for CPPC and currently only held back > by the generic cpufreq interface. >=20 > It currently only sets desired freq, it has information for > min/guaranteed, and once we get thermal intergrated we might have > sensible data for max freq too. >=20 Will do. > > TODO: > > * Create a linux userspace tool that will help users generate a CPPC pr= ofile > > for their target workload. >=20 > Basically a big fat NAK for this approach to cpufreq. >=20 Is that for exposing the sysfs interface, having a stub driver, or both? Would it be better to have a cpufreq driver that implements some policy rat= her than just providing the sysfs interface? > > * Create a general CPPC policy in the kernel. >=20 > We already have that, sorta. Right, but it seems to still be focused on CPU frequency rather than abstra= ct performance like how CPPC is defined. This is another reason for exposing the CPPC interface directly. We'll give= users the ability to interact with the platform, using CPPC, without havin= g to follow the CPUFREQ paradigm. Do you think this is doable? Or should we always have some kernel interacti= on because of the scheduler, etc.? Thanks, Yazen